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公开(公告)号：US20120162189A1
公开(公告)日：2012-06-28
申请号：US13412258
申请日：2012-03-05
CPC分类号： H03K19/018514 , H03K19/00361 , H04L25/0276
摘要： In a driver circuit in a transmission system, an output circuit outputs a differential signal based on input data signals. A current source control circuit controls a constant current source so that a common-mode potential of the differential signal becomes equal to a predetermined reference potential. An overshoot reduction circuit is connected to an input line of the common-mode potential of the current source control circuit, and reduces an overshoot of the common-mode potential based on the control signal.
摘要翻译： 在传输系统的驱动电路中，输出电路基于输入数据信号输出差分信号。 电流源控制电路控制恒流源，使得差分信号的共模电位变得等于预定的参考电位。 过冲减少电路连接到电流源控制电路的共模电位的输入线，并且基于控制信号减小共模电位的过冲。
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2.发明申请DRIVER CIRCUIT, RECEIVER CIRCUIT, AND METHOD OF CONTROLLING A COMMUNICATIONS SYSTEM INCLUDING THE CIRCUITS 有权驱动电路，接收电路和控制包括电路的通信系统的方法公开(公告)号：US20110268198A1
公开(公告)日：2011-11-03
申请号：US13143233
申请日：2010-11-01
IPC分类号： H04L25/00
CPC分类号： H04B1/1615 , H04L25/0272
摘要： In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
摘要翻译： 在用于差分信号的通信系统中，驱动电路通过一对差分信号线连接到接收器电路。 当不发送数据时，差分信号线保持在预定电位，并且当数据要被传送时，以预定电位输出差分信号。 当检测到差分信号线的电位的状态时，接收器电路在掉电状态和正常状态之间切换。
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公开(公告)号：US20110241432A1
公开(公告)日：2011-10-06
申请号：US13139397
申请日：2010-11-01
IPC分类号： H02J4/00
CPC分类号： G06F13/42 , H04L25/0272 , Y10T307/696
摘要： To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal.A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.
摘要翻译： 为了提供支持单端方法和差分方法两者的接口电路作为传输方法，并且用于差分信号的一对输入端子被共享以输入/输出单端信号。 当将差分信号输入到与一对共享终端不同的差分信号的一对专用输入端子时，接收通过一对共享端子输入的差分信号的差分信号接收电路被激活。 在差分信号接收电路被激活之后，由内置控制器维持有效状态。 因此，通过控制通过一对专用输入端子输入的差分信号来控制接收通过共享端子输入的差分信号的差分信号接收电路的激活，此外，差分信号接收电路在 意想不到的时间降到了低水平。
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4.发明授权LSI core including voltage generation circuit and system LSI including the LSI core 有权LSI核心，包括具有LSI核心的电压产生电路和系统LSI公开(公告)号：US06356144B1
公开(公告)日：2002-03-12
申请号：US09580139
申请日：2000-05-30
IPC分类号： H01L2500
CPC分类号： G06F13/4086 , H01L2224/05554
摘要： An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.
摘要翻译： LSI核心包括第一终端; 第二个终端 以及用于产生电压的电压产生电路。 第一端子连接到设置在LSI核心外部的第一外部线路。 第二端子连接到第一外部线路和连接到设置在LSI核心外部的第二外部线路。 电压产生电路包括用于产生电压的电压产生部分，用于通过第一端子将由电压产生部分产生的电压输出到第一外部线路的输出部分和用于接收电压的输入部分，输出到第一 外部线由输出部分，通过第二个外部线路和第二个终端。
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公开(公告)号：US08665872B2
公开(公告)日：2014-03-04
申请号：US13064469
申请日：2011-03-28
申请人： Yoshihide Komatsu
发明人： Yoshihide Komatsu
IPC分类号： H04L12/28
CPC分类号： H04L12/42 , H04L12/4641
摘要： When a packet received from a ring network is addressed to a device on a local network established under a transmission apparatus, then that transmission apparatus detects whether a memory device installed therein is in the memory full state. If the memory device is determined to be in the memory full state, then the transmission apparatus sends the packet, which was received from the ring network, back to the ring network. Subsequently, when the memory device recovers from the memory full state, the transmission apparatus sends the packet to the specified device in the local network.
摘要翻译： 当从环形网络接收的分组被寻址到在传输设备下建立的本地网络上的设备时，该传输设备检测其中安装的存储设备是否处于存储器满状态。 如果确定存储器件处于存储器满状态，则发送装置将从环形网络接收到的数据包发回环网。 随后，当存储器装置从存储器完全状态恢复时，发送装置将分组发送到本地网络中的指定装置。
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公开(公告)号：US07020817B2
公开(公告)日：2006-03-28
申请号：US10159024
申请日：2002-06-03
申请人： Yoshihide Komatsu
发明人： Yoshihide Komatsu
IPC分类号： G01R31/28
CPC分类号： G01R31/31922 , G01R31/31937
摘要： The delay characteristic of a chip under test on which a function test is performed first is detected by performing an edge search for stabilizing the test without awaiting the delay characteristic to be stabilized and the result of detection is stored in a memory. By using the delay characteristic stored in the memory, the function test is performed repeatedly on the chip under test till NG (FAIL) occurs. When NG occurs, the function test is performed repeatedly till the NG count of the chip under test reaches a first specified number. If the NG count exceeds the first specified number, the foregoing process is repeated starting from the edge search. If the NG count reaches a second specified number, the chip under test is determined to be defective and the test is ended.
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7.发明申请公开(公告)号：US20050201375A1
公开(公告)日：2005-09-15
申请号：US11122381
申请日：2005-05-05
IPC分类号： H04L12/28
CPC分类号： H04L43/50 , H04L1/0045 , H04L1/1893 , H04L41/0677 , H04L2001/0096
摘要： An uninterruptible transfer can be realized during a line failure in a transmission system performing a packet transmission between transmitting apparatuses connected via a plurality of lines. In a method for realizing the uninterruptible transfer, test packets including information of the number of packets received from the transmitting apparatus of a destination are periodically sent to the transmitting apparatus of a source. The transmitting apparatus of the source compares the received information of the number of packets included in the received test packets with the number of packets sent out to the transmitting apparatus of the destination via one line. When the comparison shows a disagreement between the number of the received packets and the number of the sent-out packets, packets corresponding to the disagreement are resent to the transmitting apparatus of the destination via another line. The packets, before being sent out to the transmitting apparatus of the destination, are stored in a buffer memory. When the comparison shows an agreement between the number of the received packets and the number of the sent-out packets, packets, which are stored in the buffer memory, corresponding to the agreement are released from the buffer memory.
摘要翻译： 在通过多条线路连接的发送装置之间执行分组传输的传输系统的线路故障期间，可以实现不间断传送。 在实现不间断传送的方法中，周期性地向源的发送装置发送包括从目的地的发送装置接收的分组数量的信息的测试分组。 源的发送装置将接收到的测试分组中包含的分组数量的接收信息与经由一行发送到目的地的发送装置的分组的数量进行比较。 当比较表示接收到的分组数与发送分组的数量之间存在分歧时，对应于不一致的分组通过另一行重新发送到目的地的发送装置。 在发送到目的地的发送装置之前，分组被存储在缓冲存储器中。 当比较表示接收到的数据包的数量和发送数据包的数量之间的一致性时，从缓冲存储器释放对应于协议的存储在缓冲存储器中的数据包。
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公开(公告)号：US06633588B1
公开(公告)日：2003-10-14
申请号：US09410764
申请日：1999-10-01
申请人： Tadahiro Yoshida , Hiroyuki Yamauchi , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
发明人： Tadahiro Yoshida , Hiroyuki Yamauchi , Hironori Akamatsu , Satoshi Takahashi , Yutaka Terada , Yukio Arima , Takashi Hirata , Yoshihide Komatsu
IPC分类号： G06F1516
CPC分类号： G06F13/4265 , Y02D10/14 , Y02D10/151
摘要： First and second nodes are coupled together by a bus. The first node includes a detecting circuit for detecting the maximum data transfer capability of a connected node, at least two receiving circuits for receiving data from the bus, and a controlling circuit for selecting, based on an output signal from the detecting circuit and for optimizing the configuration of a receiving unit so as to bring the other of the receiving circuits to a stop. The second node includes a transmitting circuit for transmitting data to the bus and a notifying circuit for notifying the first node of its own maximum transfer capability.
摘要翻译： 第一和第二节点通过总线耦合在一起。 第一节点包括用于检测连接节点的最大数据传输能力的检测电路，用于从总线接收数据的至少两个接收电路，以及用于基于来自检测电路的输出信号进行优化的控制电路 接收单元的配置，以使另一个接收电路停止。 第二节点包括用于向总线发送数据的发送电路和用于通知第一节点自己的最大传输能力的通知电路。
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公开(公告)号：US06262568B1
公开(公告)日：2001-07-17
申请号：US09734191
申请日：2000-12-12
IPC分类号： G05F304
CPC分类号： G05F3/205
摘要： An inventive potential generator generates a predetermined potential and includes first operational amplifier, current supply circuit and current sink circuit. A first reference potential is applied to the non-inverting input terminal of the first amplifier and a potential at the output node of the first amplifier is not only applied to the inverting input terminal of the first amplifier but also used as the output of the generator. The current supply circuit supplies a current to the output node of the first amplifier if the potential at the output node of the first amplifier is lower than a predefined level. And the current sink circuit drains a current from the output node of the first amplifier if the potential at the output node of the first amplifier is higher than the predefined level.
摘要翻译： 本发明的潜在发生器产生预定电位并且包括第一运算放大器，电流供应电路和电流吸收电路。 第一参考电位被施加到第一放大器的非反相输入端，并且第一放大器的输出节点处的电位不仅被施加到第一放大器的反相输入端，而且还用作发生器的输出 。 如果第一放大器的输出节点处的电位低于预定义电平，则电流供应电路向第一放大器的输出节点提供电流。 并且如果第一放大器的输出节点处的电位高于预定义电平，则电流吸收电路从第一放大器的输出节点漏出电流。
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公开(公告)号：US08713231B2
公开(公告)日：2014-04-29
申请号：US13139397
申请日：2010-11-01
IPC分类号： G06F13/42
CPC分类号： G06F13/42 , H04L25/0272 , Y10T307/696
摘要： To aim to provide an interface circuit that supports both a single-ended method and a differential method as a transmission method, and one of pairs of input terminals for a differential signal is shared to input/output a single-ended signal.A differential signal receiving circuit that receives a differential signal input through the pair of shared terminals is activated when a differential signal is input to a pair of dedicated input terminals for a differential signal, which is different from the pair of shared terminals. After the differential signal receiving circuit is activated, the active state is maintained by a built-in controller.Accordingly, the activation of the differential signal receiving circuit that receives a differential signal input through the shared terminals is controlled by controlling the differential signal input through the pair of dedicated input terminals, and furthermore, the possibility that the differential signal receiving circuit becomes inactive at an unexpected timing is reduced to a low level.
摘要翻译： 为了提供支持单端方法和差分方法两者的接口电路作为传输方法，并且用于差分信号的一对输入端子被共享以输入/输出单端信号。 当将差分信号输入到与一对共享终端不同的差分信号的一对专用输入端子时，接收通过一对共享端子输入的差分信号的差分信号接收电路被激活。 在差分信号接收电路被激活之后，由内置控制器维持有效状态。 因此，通过控制通过一对专用输入端子输入的差分信号来控制接收通过共享端子输入的差分信号的差分信号接收电路的激活，此外，差分信号接收电路在 意想不到的时间降到了低水平。
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