发明授权
- 专利标题: Delay element calibration
- 专利标题(中): 延迟元件校准
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申请号: US10856907申请日: 2004-05-27
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公开(公告)号: US07024324B2公开(公告)日: 2006-04-04
- 发明人: Michael C. Rifani , Keng L. Wong , Christopher Pan
- 申请人: Michael C. Rifani , Keng L. Wong , Christopher Pan
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 主分类号: G06F19/00
- IPC分类号: G06F19/00
摘要:
A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.
公开/授权文献
- US20050278131A1 Delay element calibration 公开/授权日:2005-12-15
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