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    Delay element calibration
    1.
    发明授权
    Delay element calibration 失效
    延迟元件校准

    公开(公告)号：US07024324B2

    公开(公告)日：2006-04-04

    申请号：US10856907

    申请日：2004-05-27

    申请人： Michael C. Rifani ,  Keng L. Wong ,  Christopher Pan

    发明人： Michael C. Rifani ,  Keng L. Wong ,  Christopher Pan

    IPC分类号： G06F19/00

    CPC分类号： G01R29/0273

    摘要： A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.

    摘要翻译： 本文描述了用于校准延迟元件的方法。 在一些实施例中，该方法可以包括用时钟沿生成时钟信号，使用可调延迟线产生具有参考边沿的参考信号以延迟时钟信号，以及延迟选定的一个时钟信号和参考信号通过 具有阵列延迟的阵列延迟元件的阵列延迟线。 在一些实施例中，该方法还可以包括调整可调延迟线以获得第一可调延迟，使得时钟和参考边沿在阵列延迟元件的一侧对准，调节可调延迟线以获得第二可调延迟 时钟和参考边沿在阵列延迟元件的另一侧对准，并且确定第一和第二可调延迟之间的延迟差以确定由阵列延迟元件提供的阵列延迟的值。 本发明的其它实施例可以包括但不限于适于促进实施上述方法的装置和系统。

    Controlling sequence of clock distribution to clock distribution domains
    3.
    发明授权
    Controlling sequence of clock distribution to clock distribution domains 有权
    控制时钟分配到时钟分配域的顺序

    公开(公告)号：US07386749B2

    公开(公告)日：2008-06-10

    申请号：US11073294

    申请日：2005-03-04

    申请人： Michael C. Rifani ,  Vaughn J. Grossnickle ,  Keng L. Wong

    发明人： Michael C. Rifani ,  Vaughn J. Grossnickle ,  Keng L. Wong

    IPC分类号： G06F1/12 ,  G06F1/14 ,  G06F1/00

    CPC分类号： G06F1/10

    摘要： An embodiment of the present invention is a technique to control clock distribution to a circuit. A scheduler schedules a sequence of a clock distribution of clock signals to a plurality of clock distribution domains (CKDOMs) in the circuit according to a state status of the circuit. A controller controls enabling the clock distribution to the CKDOMs according to the scheduled sequence.

    摘要翻译： 本发明的一个实施例是一种控制电路的时钟分配的技术。 调度器根据电路的状态将时钟信号的时钟分布序列调度到电路中的多个时钟分配域（CKDOM）。 控制器根据调度顺序控制对CKDOM的时钟分配。

    Data transfer between asynchronous clock domains
    4.
    发明授权
    Data transfer between asynchronous clock domains 有权

    公开(公告)号：US10025343B2

    公开(公告)日：2018-07-17

    申请号：US13991602

    申请日：2011-12-28

    申请人： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

    发明人： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

    IPC分类号： G06F1/12 ,  G06F13/42

    摘要： Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

    DATA TRANSFER BETWEEN ASYNCHRONOUS CLOCK DOMAINS
    6.
    发明申请
    DATA TRANSFER BETWEEN ASYNCHRONOUS CLOCK DOMAINS 有权
    非同步时钟域之间的数据传输

    公开(公告)号：US20130254583A1

    公开(公告)日：2013-09-26

    申请号：US13991602

    申请日：2011-12-28

    申请人： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

    发明人： Michael C. Rifani ,  Alan B. Kyker ,  Alan S. Geist ,  David M. Lee

    IPC分类号： G06F1/12

    CPC分类号： G06F1/12 ,  G06F13/4291

    摘要： Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.

    摘要翻译： 本文公开的一些实施例提供了用于在异步时钟域之间传送数据的技术和布置。 可以由第一时钟域产生同步信号，并且响应于同步信号可以在域之间传送数据。 可以与同步信号相比较来监视第二时钟域的时钟周期，以报告每次出现同步信号时出现的第二时钟域周期数。 该信息可以通过测试和验证设备来记录，以便于错误分析。

    Closed-loop independent DLL-controlled rise/fall time control circuit
    8.
    发明授权
    Closed-loop independent DLL-controlled rise/fall time control circuit 有权
    闭环独立DLL控制上升/下降时间控制电路

    公开(公告)号：US07038512B2

    公开(公告)日：2006-05-02

    申请号：US10877991

    申请日：2004-06-29

    申请人： Timothy M Wilson ,  Michael C. Rifani ,  Songmin Kim ,  Greg Taylor

    发明人： Timothy M Wilson ,  Michael C. Rifani ,  Songmin Kim ,  Greg Taylor

    IPC分类号： H03K5/12

    CPC分类号： H03K5/01 ,  H03K2005/00039

    摘要： A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

    摘要翻译： 用于处理信号的系统和方法确定驱动信号的上升和下降时间，将上升和下降时间与期望值进行比较，并且独立地将上升和下降时间控制为等于期望值。 上升和下降时间可以通过基于上升时间和所需值之间的差异产生一个或多个第一校正位来控制，基于下降时间和下降时间之间的差产生一个或多个第二校正位 对应一个期望值，然后分别施加位以独立地控制驱动信号的上升和下降时间。 驱动信号可以是I / O信号或其他类型的信号。