Method of fabricating a semiconductor package and semiconductor package containing an integrated circuit chip having, on one front face, electrical connection regions, in which a first multilayer plate (2) comprising an assembly face (2a) is furnished with an adhesive layer (8) and which has through-holes (9); and a second plate (3) has a recess (13) made in one assembly face (3a) fastened to the assembly face of the first plate via the said adhesive layer; the said chip (4) being placed in the said recess in a position such that its front face is fastened to the assembly face of the first plate via the said adhesive layer and that its electrical connection regions are located facing the through-holes of this first plate, and the bottom of the recess of the said second plate bearing against the rear face of the chip opposite the front face.