Invention Grant
US07033895B2 Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process 有权
使用选择性外延生长工艺制造具有升高的源极/漏极结构的MOS晶体管的方法

Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process
Abstract:
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
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