Invention Grant
US07033895B2 Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process
有权
使用选择性外延生长工艺制造具有升高的源极/漏极结构的MOS晶体管的方法
- Patent Title: Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process
- Patent Title (中): 使用选择性外延生长工艺制造具有升高的源极/漏极结构的MOS晶体管的方法
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Application No.: US10823420Application Date: 2004-04-13
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Publication No.: US07033895B2Publication Date: 2006-04-25
- Inventor: Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
- Applicant: Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Mills & Onello, LLP
- Priority: KR10-2003-0030614 20030514
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
Public/Granted literature
- US20040227164A1 MOS transistor with elevated source/drain structure and method of fabricating the same Public/Granted day:2004-11-18
Information query
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