Invention Grant
- Patent Title: Testing methodology and apparatus for interconnects
- Patent Title (中): 互连测试方法和设备
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Application No.: US10319517Application Date: 2002-12-16
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Publication No.: US07047458B2Publication Date: 2006-05-16
- Inventor: Jay Nejedlo , Sean R. Babcock
- Applicant: Jay Nejedlo , Sean R. Babcock
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G01R31/28
Abstract:
A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.
Public/Granted literature
- US20040117709A1 Testing methodology and apparatus for interconnects Public/Granted day:2004-06-17
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