- 专利标题： Dynamic gate with conditional keeper for soft error rate reduction
-
申请号： US10107779申请日： 2002-03-26
-
公开(公告)号： US07053663B2公开(公告)日： 2006-05-30
- 发明人: Peter Hazucha , Atila Alvandpour , Ram Krishnamurthy , Tanay Karnik
- 申请人： Peter Hazucha , Atila Alvandpour , Ram Krishnamurthy , Tanay Karnik
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Jeffrey B. Huter
- 主分类号： H03K19/096
- IPC分类号： H03K19/096
摘要：
A dynamic logic gate with a conditional keeper, the conditional keeper comprising a pMOSFET pull-up that switches ON only after the dynamic logic gate completes an evaluation so as to avoid contention with the pull-down network. By sizing the conditional keeper to be stronger than the half-keeper, embodiments may realize a significant reduction in soft error rates that are latched.
公开/授权文献
信息查询
IPC分类:
