公开(公告)号：US06751141B1

公开(公告)日：2004-06-15

申请号：US10305703

申请日：2002-11-26

Applicant: Atila Alvandpour ,  Manoj Sinha ,  Ram K. Krishnamurthy

Inventor： Atila Alvandpour ,  Manoj Sinha ,  Ram K. Krishnamurthy

IPC: G11C702

CPC classification number: G11C7/065 ,  G11C7/12

Abstract: A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.

Abstract translation: 一种用于读取SRAM中的存储单元的读出放大器，读出放大器包括两个栅极偏置的pMOSFET，每个对应于选定的位线。 两个栅极偏置的pMOSFET的栅极将其栅极偏置到偏置电压，其源极通过列选择晶体管耦合到所选位线，并且其漏极通过传输晶体管耦合到两个交叉耦合的反相器的两个端口， 交叉耦合的逆变器形成锁存器。 在选择的位线对已被预充电并且预充电阶段结束之后，两个栅极偏置的pMOSFET中的一个快速进入其亚阈值区域，其中一个位线通过其相应的存储单元放电，从而切断位线的电容 从感测放大器。 当通过晶体管使能时，两个pMOSFET中的另一个允许显着的位线电荷通过其对应的传输晶体管传输到其相应的端口，而相对较小的电荷被传送到另一个端口。 该电荷转移方案允许在端口处快速产生差分电压，从而以降低的功率消耗提供快速锁存和读取操作。 位线电压摆幅也可以降低以降低功耗。

公开(公告)号：US06690205B2

公开(公告)日：2004-02-10

申请号：US10283933

申请日：2002-10-29

Applicant: Atila Alvandpour

Inventor： Atila Alvandpour

IPC: H03K1901

CPC classification number: H03K19/0963

Abstract: A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

Abstract translation: 包含在集成电路内的多米诺逻辑电路包括动态逻辑电路和中间逻辑电路。 中间逻辑电路包括具有耦合到源电压线的源极端子和具有连接到低接地电压线的源极端子的n块晶体管的上拉晶体管。

公开(公告)号：US06617890B1

公开(公告)日：2003-09-09

申请号：US10104393

申请日：2002-03-22

Applicant: Tsung-Hao Chen ,  Peter Hazucha ,  Atila Alvandpour ,  Tanay Karnik ,  Chung-Ping Chen

Inventor： Tsung-Hao Chen ,  Peter Hazucha ,  Atila Alvandpour ,  Tanay Karnik ,  Chung-Ping Chen

IPC: H03K5153

CPC classification number: G01R19/16538 ,  G06F1/28 ,  H03K5/08 ,  H03K5/153

Abstract: A system for measuring the stability of a power signal from a power supply includes a threshold violation detector. The threshold violation detector includes a comparator and an indicator. The comparator has a power signal input, a threshold signal input, and a comparison result output, and is configured to compare the power signal on the power signal input with a threshold on the threshold signal input to present a comparison result signal on the comparison result output. The indicator has a threshold violation output and a comparison input that receives the comparison result signal from the comparator. The indicator presents a threshold violation signal on the threshold violation output when the comparison result signal indicates that the power signal has violated the threshold.

Abstract translation: 用于测量来自电源的功率信号的稳定性的系统包括阈值违规检测器。 阈值违规检测器包括比较器和指示器。 比较器具有功率信号输入，阈值信号输入和比较结果输出，并且被配置为将功率信号输入上的功率信号与阈值信号输入上的阈值进行比较，以在比较结果上呈现比较结果信号 输出。 指示器具有阈值违反输出和比较输入，其从比较器接收比较结果信号。 当比较结果信号指示电源信号已经违反阈值时，指示器在阈值违反输出上呈现阈值违反信号。

公开(公告)号：US06493254B1

公开(公告)日：2002-12-10

申请号：US09896348

申请日：2001-06-28

Applicant: Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

Inventor： Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

IPC: G11C1140

CPC classification number: G11C11/412

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

Abstract translation: 本发明的实施例涉及具有重负载位线的存储器电路，并且其中读取访问或传输晶体管中的漏电流的影响减小或漏电流减小。

公开(公告)号：US06388940B1

公开(公告)日：2002-05-14

申请号：US09672177

申请日：2000-09-27

Applicant: Atila Alvandpour ,  Ganesh Balamurugan ,  Krishnamurthy Soumyanath

Inventor： Atila Alvandpour ,  Ganesh Balamurugan ,  Krishnamurthy Soumyanath

IPC: G11C800

CPC classification number: G11C7/12 ,  G11C11/419

Abstract: A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.

Abstract translation: 一种新颖的电路技术，用于减小通过大寄存器堆的读路径的漏电流，其中在栅极读取晶体管和局部位线之间的临界传输晶体管上施加负栅极 - 源极电压，使得当单元处于第一 状态，来自单元读取晶体管的动态节点的漏电流减小。 减小的漏电流增加了读操作的鲁棒性和性能。

公开(公告)号：US06919737B2

公开(公告)日：2005-07-19

申请号：US10010737

申请日：2001-12-07

Applicant: Atila Alvandpour ,  Ram K. Krishnamurthy

Inventor： Atila Alvandpour ,  Ram K. Krishnamurthy

IPC: H03K19/0185 ,  H03K19/0175

CPC classification number: H03K19/018521

Abstract: A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.

Abstract translation: 描述电压电平转换器和将第一逻辑电压电平转换到第二逻辑电压电平的方法。 在一个实施例中，电压电平转换器将连接到第一电源电压的第一逻辑单元连接到与第二电源电压连接的第二逻辑单元。 电压电平转换器包括连接到第二电源电压的至少一个晶体管。 所述至少一个晶体管具有其绝对值大于或等于所述第二电源电压和所述第一电源电压之间的差的绝对值的阈值电压。 在替代实施例中，用于将第一逻辑电压电平转换为第二逻辑电压电平的方法包括从具有在第一电压电平和第二电压电平之间的输出电压摆幅的逻辑单元传输逻辑信号，接收逻辑信号 在具有上拉晶体管的逻辑电路和在第三电压电平和第四电压电平之间的输出电压摆幅，并且当所述逻辑信号具有略大于所述第三电压 电平和第一电压电平。

公开(公告)号：US06590801B2

公开(公告)日：2003-07-08

申请号：US10172106

申请日：2002-06-13

Applicant: Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

Inventor： Atila Alvandpour ,  Ram K. Krishnamurthy ,  Siva G. Narendra

IPC: G11C1140

CPC classification number: G11C11/412

Abstract: Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

公开(公告)号：US06559492B1

公开(公告)日：2003-05-06

申请号：US10010705

申请日：2001-11-07

Applicant: Peter Hazucha ,  Atila Alvandpour

Inventor： Peter Hazucha ,  Atila Alvandpour

IPC: H01L27108

CPC classification number: H02M3/07

Abstract: A DC-to-DC switching power converter includes switching elements having capacitive gate control inputs, an energy storage element and driver circuitry. Improved efficiency is achieved using adiabatic buffers to drive MOSFET switching elements with stepped switching signals. Substantially equal rise and fall times are achieved. In one embodiment, the switching power converter is fabricated on a semiconductor die to generate an output voltage to one or more functional unit blocks on the die.

Abstract translation: DC-DC开关功率转换器包括具有电容性栅极控制输入的开关元件，能量存储元件和驱动器电路。 使用绝热缓冲器来实现提高效率，以驱动具有阶梯式开关信号的MOSFET开关元件。 实现了相当大的上升和下降时间。 在一个实施例中，开关功率转换器制造在半导体管芯上以产生对管芯上的一个或多个功能单元块的输出电压。

公开(公告)号：US06549040B1

公开(公告)日：2003-04-15

申请号：US09608683

申请日：2000-06-29

Applicant: Atila Alvandpour ,  Krishnamurthy Soumyanath ,  Ram K. Krishnamurthy

Inventor： Atila Alvandpour ,  Krishnamurthy Soumyanath ,  Ram K. Krishnamurthy

IPC: H03K19096

CPC classification number: H03K19/0963

Abstract: A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.

Abstract translation: 一种电路，包括输入时钟信号以接收时钟信号，输入至少一个数据信号以接收至少一个数据信号，以及多输入条件反相器以接收时钟信号和数据信号，并产生动态输出。 电路还包括条件保持器电路，用于在时钟评估和动态输出为高时为动态输出节点充电。

公开(公告)号：US06498514B2

公开(公告)日：2002-12-24

申请号：US09846519

申请日：2001-04-30

Applicant: Atila Alvandpour

Inventor： Atila Alvandpour

IPC: H03K1901

CPC classification number: H03K19/0963

Abstract: A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.

Abstract translation: 包含在集成电路内的多米诺逻辑电路包括动态逻辑电路和中间逻辑电路。 中间逻辑电路包括具有耦合到源电压线的源极端子和具有连接到低接地电压线的源极端子的n块晶体管的上拉晶体管。