- 专利标题: Test circuit for delay lock loops
-
申请号: US10949583申请日: 2004-09-24
-
公开(公告)号: US07061224B2公开(公告)日: 2006-06-13
- 发明人: Akira Kakizawa , Mark Beiley , Mamun Ur Rashid
- 申请人: Akira Kakizawa , Mark Beiley , Mamun Ur Rashid
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 主分类号: G01R23/175
- IPC分类号: G01R23/175 ; H03L7/06
摘要:
A method of testing a delay lock loop circuit is provided which comprises receiving an input signal and configuring the delay lock loop to generate a delay lock loop output signal based on the input signal. The method further comprises generating a test output signal from the input signal and delay lock loop output signal indicative of a relationship between a transition on the input signal and a transition on delay lock loop output signal.
公开/授权文献
- US20060066291A1 Test circuit for delay lock loops 公开/授权日:2006-03-30
信息查询