- 专利标题: Method for modeling and processing asynchronous functional specification for system level architecture synthesis
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申请号: US09947250申请日: 2001-09-05
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公开(公告)号: US07076417B2公开(公告)日: 2006-07-11
- 发明人: Rajiv Jain , Alan Peisheng Su , Chaitali Biswas
- 申请人: Rajiv Jain , Alan Peisheng Su , Chaitali Biswas
- 申请人地址: US CA Santa Clara
- 专利权人: Agilent Technologies, Inc.
- 当前专利权人: Agilent Technologies, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06F9/45
- IPC分类号: G06F9/45
摘要:
A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.
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