公开(公告)号：US20120110525A1

公开(公告)日：2012-05-03

申请号：US12973956

申请日：2010-12-21

申请人： Alan Peisheng SU

发明人： Alan Peisheng SU

IPC分类号： G06F17/50

CPC分类号： G06F17/5027

摘要： A hybrid electronic design system and a reconfigurable connection matrix thereof are disclosed. The electronic design system includes a virtual unit, a hybrid unit and a communication channel. The virtual unit further includes a plurality of proxy units, a plurality of virtual components and a driver. The virtual components are connected with the driver via the proxy units. The hybrid unit further includes an emulate unit, a physical unit and a chip level transactor. The chip level transactor is connected with the emulate unit and the physical unit. The communication channel is connected with the driver of the virtual unit and the chip level transactor of the hybrid unit.

摘要翻译： 公开了一种混合电子设计系统及其可重构连接矩阵。 电子设计系统包括虚拟单元，混合单元和通信信道。 虚拟单元还包括多个代理单元，多个虚拟组件和驱动程序。 虚拟组件通过代理单元与驱动程序连接。 混合单元还包括仿真单元，物理单元和芯片级交换器。 芯片级交换机与仿真单元和物理单元连接。 通信信道与混合单元的虚拟单元的驱动器和芯片级交换器连接。

公开(公告)号：US07076417B2

公开(公告)日：2006-07-11

申请号：US09947250

申请日：2001-09-05

申请人： Rajiv Jain ,  Alan Peisheng Su ,  Chaitali Biswas

发明人： Rajiv Jain ,  Alan Peisheng Su ,  Chaitali Biswas

IPC分类号： G06F9/45

CPC分类号： G06F8/10 ,  G06F17/5022 ,  G06F17/5045

摘要： A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.

公开(公告)号：US07031887B2

公开(公告)日：2006-04-18

申请号：US09918734

申请日：2001-07-31

申请人： Rajiv Jain ,  Alan Peisheng Su ,  Chaitali Biswas

发明人： Rajiv Jain ,  Alan Peisheng Su ,  Chaitali Biswas

IPC分类号： G06F17/50

CPC分类号： G06F9/5066 ,  G06F2209/5017

摘要： A method is provided for exploring alternative architectures for partitioning computer system resources to execute multiple task specifications. An initial master task graph is formed from the multiple task specifications, the initial master task graph including at least one hierarchical task with pointers to either AND sub-task graphs or XOR sub-task graphs. The initial master task graph is processed to provide a selected number of final master task graphs, each of the final master task graphs comprising a list of AND task graphs. A family of architectures is generated for each of the final master task graphs, each of the architectures generated for a given master task graph being capable of executing every AND task graph included therein. The degree of resemblance in composition, functional capability or performance resulting between architectures from different master task graphs is a function of the correlation between the contents of these master task graphs and not of concern to the user of the aforementioned method.