Invention Grant
- Patent Title: Method for manufacturing semiconductor device having thick insulating layer under gate side walls
- Patent Title (中): 在栅极侧壁上具有厚绝缘层的半导体器件的制造方法
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Application No.: US11136419Application Date: 2005-05-25
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Publication No.: US07078303B2Publication Date: 2006-07-18
- Inventor: Masahiro Yoshida , Shunichi Tokitoh
- Applicant: Masahiro Yoshida , Shunichi Tokitoh
- Applicant Address: JP Tokyo
- Assignee: Oki Electric Industry Co., Ltd.
- Current Assignee: Oki Electric Industry Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: VolentineFrancos&Whitt PLLC
- Priority: JP2000-010250 20000117
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8238

Abstract:
A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.
Public/Granted literature
- US20050221562A1 Method for manufacturing semiconductor device having thick insulating layer under gate side walls Public/Granted day:2005-10-06
Information query
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