公开(公告)号：US07675175B2

公开(公告)日：2010-03-09

申请号：US11150107

申请日：2005-06-13

Applicant: Shunichi Tokitoh ,  Seiichi Kondou ,  Bo Un Yoon

Inventor： Shunichi Tokitoh ,  Seiichi Kondou ,  Bo Un Yoon

IPC: H01L23/48

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. An upper layer barrier layer made from a conductive barrier material film is formed on an interlayer insulating film groove sidewall of the semiconductor device. Embedded in the groove is an upper layer seal ring wiring line with thickness of approximately 10 micrometers for instance, in which a plurality of isolated pockets of insulators are disbursed. These isolated pockets of insulators are formed using the interlayer insulating film which forms the damascene wiring line. Additionally, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in an element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have damascene wiring structures.

Abstract translation: 具有镶嵌线结构的半导体器件，其可以防止密封环与布线或电极垫之间的短路。 在半导体器件的层间绝缘膜槽侧壁上形成由导电阻挡材料膜制成的上层阻挡层。 嵌入凹槽中的是上层密封环布线，例如厚度约为10微米，其中多个隔离的绝缘体袋被分配。 使用形成镶嵌线的层间绝缘膜形成这些隔离的绝缘体袋。 此外，在元件形成区域中形成第一上层槽布线和第二上层槽布线，并且在外周上形成上层阻挡层。 上层密封环布线和两层上层布线都具有镶嵌布线结构。

公开(公告)号：US20080157285A1

公开(公告)日：2008-07-03

申请号：US11931234

申请日：2007-10-31

Applicant: Shunichi Tokitoh

Inventor： Shunichi Tokitoh

IPC: H01L23/52

CPC classification number: H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.

Abstract translation: 半导体器件包括其上限定有元件区域和外围区域的衬底。 在元件区域中至少提供一个功能元件，并且周边区域围绕元件区域。 半导体器件还包括一层布线。 半导体器件还包括密封环，该密封环具有设置在与布线层相同的层中的周边区域中的环形部分。 环部具有围绕芯片区域的主体和从密封环主体朝向元件区域突出的多个部分。

公开(公告)号：US07125794B2

公开(公告)日：2006-10-24

申请号：US10940820

申请日：2004-09-15

Applicant: Seiichi Kondo ,  Kaori Misawa ,  Shunichi Tokitoh ,  Takashi Nasuno

Inventor： Seiichi Kondo ,  Kaori Misawa ,  Shunichi Tokitoh ,  Takashi Nasuno

IPC: H01L21/4763 ,  H01L21/312 ,  H01L21/469

CPC classification number: H01L21/76826 ,  H01L21/02126 ,  H01L21/02137 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835

Abstract: A first CVD dielectric layer is deposited on a surface of a semiconductor substrate. Next, low-k layers are deposited in at least two different steps to form one of a via-layer dielectric film and a wiring-layer dielectric film on the first CVD dielectric layer. Immediately after the depositions, thermal treatment is performed. A second CVD dielectric layer is deposited on the low-k layers. A groove is formed in the second CVD dielectric layer and the low-k layers. A metal layer is deposited on that structure, filling the groove. The metal layer is removed from the second CVD dielectric layer by chemical mechanical polishing.

Abstract translation: 第一CVD绝缘层沉积在半导体衬底的表面上。 接下来，在至少两个不同的步骤中沉积低k层，以在第一CVD电介质层上形成通孔层电介质膜和布线层电介质膜之一。 沉积后立即进行热处理。 在低k层上沉积第二CVD介电层。 在第二CVD介质层和低k层中形成凹槽。 在该结构上沉积金属层，填充凹槽。 金属层通过化学机械抛光从第二CVD介电层去除。

公开(公告)号：US06482732B1

公开(公告)日：2002-11-19

申请号：US09894886

申请日：2001-06-29

Applicant: Shunichi Tokitoh

Inventor： Shunichi Tokitoh

IPC: H01L214763

CPC classification number: B24B49/14 ,  H01L21/3212

Abstract: A method for polishing a semiconductor wafer, includes the steps of supplying a polishing slurry between a polishing pad and a semiconductor wafer; polishing a surface of the semiconductor wafer with the polishing pad in a CMP process; and controlling the temperature of the polishing slurry to be in a range between 2° C. to 10° C. while the semiconductor wafer is polished.

Abstract translation: 一种用于抛光半导体晶片的方法，包括以下步骤：在抛光垫和半导体晶片之间提供抛光浆料; 在CMP工艺中用抛光垫抛光半导体晶片的表面; 并且在抛光半导体晶片的同时将抛光浆料的温度控制在2℃至10℃的范围内。

公开(公告)号：US07737474B2

公开(公告)日：2010-06-15

申请号：US11931234

申请日：2007-10-31

Applicant: Shunichi Tokitoh

Inventor： Shunichi Tokitoh

IPC: H01L23/544

CPC classification number: H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, on which an element region and a peripheral region are defined. At least one function element is to be provided in the element region, and the peripheral region surrounds the element region. The semiconductor device also includes a layer of wiring. The semiconductor device also includes a seal ring having a ring portion that is provided in the peripheral region in the same layer as the wiring layer. The ring portion has a main body surrounding a chip region, and a plurality of portions protruding toward the element region from the seal ring main body.

Abstract translation: 半导体器件包括其上限定有元件区域和外围区域的衬底。 在元件区域中至少提供一个功能元件，并且周边区域围绕元件区域。 半导体器件还包括一层布线。 半导体器件还包括密封环，该密封环具有设置在与布线层相同的层中的周边区域中的环形部分。 环部具有围绕芯片区域的主体和从密封环主体朝向元件区域突出的多个部分。

公开(公告)号：US20090315184A1

公开(公告)日：2009-12-24

申请号：US12470522

申请日：2009-05-22

Applicant: Shunichi Tokitoh

Inventor： Shunichi Tokitoh

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/522 ,  H01L23/564 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05554

Abstract: Disclosed is a semiconductor device that is capable of preventing impurities such as moisture from being introduced into an active region at the time of dicing and at the time of bonding and that is capable of being easily miniaturized. The semiconductor device includes a cylindrical dummy wire having an opening for allowing a wire interconnecting a semiconductor element and an external connection terminal to pass therethrough, extending in an insulation film provided on a semiconductor layer having the semiconductor element to surround the semiconductor element, and disposed inside the external connection terminal.

Abstract translation: 公开了一种半导体器件，其能够防止诸如水分的杂质在切割时和接合时被引入活性区域并且能够容易地小型化。 半导体器件包括一个圆柱形虚设线，其具有用于允许将半导体元件和外部连接端子互连的导线穿过的开口，在设置在具有半导体元件的半导体层上的绝缘膜中延伸以围绕半导体元件， 在外部连接端子内。

公开(公告)号：US20050221562A1

公开(公告)日：2005-10-06

申请号：US11136419

申请日：2005-05-25

Applicant: Masahiro Yoshida ,  Shunichi Tokitoh

Inventor： Masahiro Yoshida ,  Shunichi Tokitoh

IPC: H01L21/336 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的氧化硅层，形成在氧化硅层上的栅电极，以及形成在氧化硅层上并与栅电极相邻的侧壁结构。 在一种构造中，侧壁结构下方的氧化硅层的厚度比栅电极下方的氧化硅层的厚度厚。

公开(公告)号：US20050087799A1

公开(公告)日：2005-04-28

申请号：US10992082

申请日：2004-11-19

Applicant: Masahiro Yoshida ,  Shunichi Tokitoh

Inventor： Masahiro Yoshida ,  Shunichi Tokitoh

IPC: H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode structure and a side wall structure. The gate insulating layer is formed on the semiconductor substrate. The gate electrode structure is formed on the gate insulating layer, and includes a lower gate electrode layer and a cap gate layer. The side wall structure includes a nitride side wall spacer, and an oxide layer formed between the semiconductor substrate and the nitride side wall spacer and between the lower gate electrode layer and the nitride side wall spacer. A thickness of the oxide layer is greater than a thickness of the gate insulating layer, so as to prevent diffusion of nitrogen from the nitride side wall spacer to the semiconductor substrate. A height of the gate electrode structure is substantially equal to a height of the side wall structure after completion of the semiconductor device.

Abstract translation: 半导体器件包括半导体衬底，栅极绝缘层，栅电极结构和侧壁结构。 栅绝缘层形成在半导体衬底上。 栅电极结构形成在栅极绝缘层上，并且包括下栅极电极层和盖栅极层。 侧壁结构包括氮化物侧壁间隔物和形成在半导体衬底和氮化物侧壁间隔物之间​​以及下部栅极电极层和氮化物侧壁间隔物之间​​的氧化物层。 氧化物层的厚度大于栅极绝缘层的厚度，以防止氮从氮化物侧壁间隔物扩散到半导体衬底。 栅电极结构的高度与半导体器件完成后的侧壁结构的高度基本相等。

公开(公告)号：US07078303B2

公开(公告)日：2006-07-18

申请号：US11136419

申请日：2005-05-25

Applicant: Masahiro Yoshida ,  Shunichi Tokitoh

Inventor： Masahiro Yoshida ,  Shunichi Tokitoh

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的氧化硅层，形成在氧化硅层上的栅电极，以及形成在氧化硅层上并与栅电极相邻的侧壁结构。 在一种构造中，侧壁结构下方的氧化硅层的厚度比栅电极下方的氧化硅层的厚度厚。

公开(公告)号：US20060001165A1

公开(公告)日：2006-01-05

申请号：US11150107

申请日：2005-06-13

Applicant: Shunichi Tokitoh ,  Seiichi Kondou ,  Bo Un Yoon

Inventor： Shunichi Tokitoh ,  Seiichi Kondou ,  Bo Un Yoon

IPC: H01L23/48

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. The upper layer barrier layer made from a conductive barrier material film is formed on the interlayer insulating film groove sidewall of the semiconductor device, an upper layer seal ring wiring line with the thickness of approximately 10 micrometers for instance made from a wiring material film is embedded in a groove, and a plurality of isolated pockets of insulators are formed to be disbursed in the upper layer seal ring wiring line. These isolated pockets of insulators formed using the interlayer insulating film which forms the aforementioned damascene wiring line. Furthermore, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in the element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have (dual) damascene wiring structures.

Abstract translation: 具有镶嵌线结构的半导体器件，其可以防止密封环与布线或电极垫之间的短路。 由导电阻挡材料膜制成的上层阻挡层形成在半导体器件的层间绝缘膜槽侧壁上，例如由布线材料膜制成的厚度约为10微米的上层密封环布线 并且在上层密封环布线中形成多个隔离的绝缘体袋。 使用形成上述镶嵌线的层间绝缘膜形成这些隔离的绝缘体袋。 此外，在元件形成区域中形成第一上层槽布线和第二上层槽布线，并且在外周上形成上层阻挡层。 上层密封环布线和两层上层布线都具有（双）镶嵌布线结构。