发明授权
- 专利标题: Bias voltage applying circuit and semiconductor memory device
- 专利标题(中): 偏置电压施加电路和半导体存储器件
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申请号: US11055641申请日: 2005-02-09
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公开(公告)号: US07088626B2公开(公告)日: 2006-08-08
- 发明人: Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
- 申请人: Yasumichi Mori , Takahiko Yoshimoto , Masahiko Watanabe , Shinsuke Anzai , Takeshi Nojima , Munetaka Masaki
- 申请人地址: JP Osaka
- 专利权人: Sharp Kabushiki Kaisha
- 当前专利权人: Sharp Kabushiki Kaisha
- 当前专利权人地址: JP Osaka
- 代理机构: Morrison & Foerster LLP
- 优先权: JP2004-031648 20040209; JP2004-349252 20041202
- 主分类号: G11C7/00
- IPC分类号: G11C7/00
摘要:
Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.
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