Invention Grant
US07091091B2 Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer
有权
非易失性存储器制造方法，其中浮置栅极层下面的电介质层与隔离沟槽的边缘和/或浮置栅极层的边缘间隔开
- Patent Title: Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer
- Patent Title (中): 非易失性存储器制造方法，其中浮置栅极层下面的电介质层与隔离沟槽的边缘和/或浮置栅极层的边缘间隔开
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Application No.: US10879782Application Date: 2004-06-28
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Publication No.: US07091091B2Publication Date: 2006-08-15
- Inventor: Yi Ding
- Applicant: Yi Ding
- Applicant Address: TW Hsin Chu
- Assignee: ProMOS Technologies Inc.
- Current Assignee: ProMOS Technologies Inc.
- Current Assignee Address: TW Hsin Chu
- Agency: MacPherson Kwok Chen & Heid LLP
- Agent Michael Shenker
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A first dielectric (120) and a first floating gate layer (130.1) are formed on a semiconductor substrate (110). The first dielectric, the first floating gate layer, and the substrate are etched to form isolation trenches (150). The first dielectric (120) is etched to pull the first dielectric away from the trench edges (150E) and/or the edges of the first floating gate layer (130E). The trench edges and/or the edges of the first floating gate layer are then oxidized. The trenches are filled with a second dielectric (210.2), which is then etched laterally adjacent to the edges of the trench and the first floating gate layer. A second floating gate layer (130.2) is formed to extend into the regions which were occupied by the second dielectric before it was etched.
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