发明授权
US07093156B1 Embedded test and repair scheme and interface for compiling a memory assembly with redundancy implementation
有权
嵌入式测试和修复方案和接口,用于编译具有冗余实现的存储器组件
- 专利标题: Embedded test and repair scheme and interface for compiling a memory assembly with redundancy implementation
- 专利标题(中): 嵌入式测试和修复方案和接口,用于编译具有冗余实现的存储器组件
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申请号: US10144020申请日: 2002-05-13
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公开(公告)号: US07093156B1公开(公告)日: 2006-08-15
- 发明人: Alex Shubat , Randall Lee Reichenbach
- 申请人: Alex Shubat , Randall Lee Reichenbach
- 申请人地址: US CA Fremont
- 专利权人: Virage Logic Corp.
- 当前专利权人: Virage Logic Corp.
- 当前专利权人地址: US CA Fremont
- 代理机构: Danamraj & Youst, P.C.
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
An embedded test and repair (ETR) scheme and interface for generating a self-test-and-repair (STAR) memory device using an integrated design environment. User interface and supporting program code is operable to provide a dialog box for defining a memory group that includes one or more memory instances, each having corresponding fuse element requirements based on its configuration data. BIST elements and a processor compiler for providing ETR functionality are also specified via suitable portions of the integrated GUI. A fuse equation is employed for computing the number of fuses for each memory instance, which equation is derived based on the memory configuration. Fuse information for each memory instance is automatically passed to a fuse compiler that generates a fuse box having an appropriate number of fuses that can accommodate the fuse requirements of the memory instances of the group.
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