公开(公告)号：US07747425B1

公开(公告)日：2010-06-29

申请号：US11593729

申请日：2006-11-07

Applicant: Vipin Kumar Tiwari ,  Manish Bhatia ,  Abhijit Ray

Inventor： Vipin Kumar Tiwari ,  Manish Bhatia ,  Abhijit Ray

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A peak current modeling method and system for modeling peak current demand of an integrated circuit (IC) block such as, e.g., a compilable memory instance. A current demand curve associated with the IC for a particular IC block event is obtained via simulation, for example. A defined time region associated with the particular IC block event is divided into multiple time segments, whereupon at least a first current value and a second current value for each time segment is obtained based on the current demand curve. Thereafter, the current demand curve is approximated, on a segment-by-segment basis, using a select approximate waveform depending on a relationship between the first and second current values.

Abstract translation: 用于建模集成电路（IC）块的峰值电流需求的峰值电流建模方法和系统，例如可编译存储器实例。 例如，通过模拟获得与特定IC块事件的IC相关联的电流需求曲线。 与特定IC块事件相关联的定义的时间区域被划分为多个时间段，因此基于当前需求曲线获得每个时间段的至少第一当前值和第二电流值。 此后，根据第一和第二电流值之间的关系，使用选择近似波形，逐段地逐次地近似当前需求曲线。

公开(公告)号：US07692964B1

公开(公告)日：2010-04-06

申请号：US11451043

申请日：2006-06-12

Applicant: Deepak Sabharwal ,  Alexander Shubat

Inventor： Deepak Sabharwal ,  Alexander Shubat

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C11/417

Abstract: A Static Random Access Memory (SRAM) cell having a source-biasing mechanism for leakage reduction. In standby mode, the cell's wordline is deselected and a source-biasing potential is provided to the cell. In read mode, the wordline is selected and responsive thereto, the source-biasing potential provided to the cell is deactivated. Upon completion of reading, the source-biasing potential is re-activated.

Abstract translation: 一种具有用于泄漏减少的源偏置机构的静态随机存取存储器（SRAM）单元。 在待机模式下，取消选择单元格的字线，并向单元提供源偏置电位。 在读取模式中，字线被选择并响应于此，提供给单元的源偏置电位被去激活。 读取完成后，源偏置电位被重新激活。

公开(公告)号：US07609550B2

公开(公告)日：2009-10-27

申请号：US12099640

申请日：2008-04-08

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C11/34

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为行列阵列的多个存储单元。 共享源线与第一对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 共享位线与第二对相邻列相关联，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合到共享位线。

公开(公告)号：US07539590B2

公开(公告)日：2009-05-26

申请号：US11403783

申请日：2006-04-13

Applicant: Niranjan Behera ,  Bruce L. Prickett, Jr.

Inventor： Niranjan Behera ,  Bruce L. Prickett, Jr.

IPC: G01R31/00 ,  G01R31/14

CPC classification number: G11C29/56 ,  G11C29/54

Abstract: A method and apparatus for testing a memory at speed. A test and repair wrapper integrated with a memory instance is operable to receive test information scanned in from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the test and repair wrapper is operable to generate address, data and command signals based on the scanned test information, wherein the signals are used for effectuating one or more tests with respect to the memory instance.

Abstract translation: 一种用于以速度测试存储器的方法和装置。 与内存实例集成的测试和修复包装器可操作以接收从内置自检和修复（BISTR）处理器扫描的测试信息。 与测试和修复包装器相关联的逻辑电路可操作以基于扫描的测试信息产生地址，数据和命令信号，其中所述信号用于实现关于存储器实例的一个或多个测试。

公开(公告)号：US07788551B2

公开(公告)日：2010-08-31

申请号：US12188892

申请日：2008-08-08

Applicant: Niranjan Behera ,  Bruce L. Prickett, Jr. ,  Yervant Zorian

Inventor： Niranjan Behera ,  Bruce L. Prickett, Jr. ,  Yervant Zorian

IPC: G06F11/00 ,  G11C7/00

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/848

Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.

Abstract translation: 一种用于修复存储器的方法和系统。 测试和修复包装器可操作地与存储器实例的输入/输出（I / O）电路集成，以形成可操作以从内置自身接收测试和修复信息的包装器I / O（WIO）块 测试和修复（BISTR）处理器。 与WIO块相关联的逻辑电路可操作地产生由BISTR处理器本地使用的用于提供修复使能控制信号的电流误差信号，以便使用冗余存储器部分修复故障存储器部分，而不必访问后处理 修复签名生成的环境。

公开(公告)号：US20080212355A1

公开(公告)日：2008-09-04

申请号：US12099640

申请日：2008-04-08

Applicant: Amit Khanuja ,  Deepak Sabharwal

Inventor： Amit Khanuja ,  Deepak Sabharwal

IPC: G11C17/00

CPC classification number: H01L27/112 ,  G11C17/12

Abstract: A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.

Abstract translation: 用于扩散可编程ROM的紧凑型共享源线和位线架构。 在一个实施例中，ROM电路或实例包括被组织为行列阵列的多个存储单元。 共享源线与第一对相邻列相关联，共享源线保持在预定级别，其中相邻列中的存储单元的源极电耦合到共享源极线。 共享位线与第二对相邻列相关联，共享位线保持在预定电平，其中相邻列中的存储单元的漏极电耦合到共享位线。

公开(公告)号：US07415641B1

公开(公告)日：2008-08-19

申请号：US10702014

申请日：2003-11-05

Applicant: Niranjan Behera ,  Bruce L. Prickett, Jr. ,  Yervant Zorian

Inventor： Niranjan Behera ,  Bruce L. Prickett, Jr. ,  Yervant Zorian

IPC: G06F11/00 ,  G11C7/00

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/44 ,  G11C29/848

Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.

Abstract translation: 一种用于修复存储器的方法和系统。 测试和修复包装器可操作地与存储器实例的输入/输出（I / O）电路集成，以形成可操作以从内置自身接收测试和修复信息的包装器I / O（WIO）块 测试和修复（BISTR）处理器。 与WIO块相关联的逻辑电路可操作地产生由BISTR处理器本地使用的用于提供修复使能控制信号的电流误差信号，以便使用冗余存储器部分修复故障存储器部分，而不必访问后处理 修复签名生成的环境。

公开(公告)号：US20060187697A1

公开(公告)日：2006-08-24

申请号：US11409610

申请日：2006-04-24

Applicant: Amit Khanuja

Inventor： Amit Khanuja

IPC: G11C17/00

CPC classification number: G11C17/12

Abstract: A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a plurality of source line segments based on the number of row banks of the array. A plurality of local source line decoder circuits corresponding to the row banks are provided for decoding a selected source line segment based on the column address as well as a Bank Select signal generated from the row address of a particular cell. Local pull-down circuitry is provided with each bank for deactivating the selected source line segment upon commencing a memory access operation.

Abstract translation: 用于减少ROM中的泄漏和功率的分区源线架构。 在一个实施例中，ROM由被组织为具有M行和N列的阵列的多个存储单元组成。 每列与预充电源线相关联，该预充电源线基于阵列的行组的数量被划分为多个源线段。 提供对应于行组的多个本地源极线解码器电路，用于基于列地址对所选择的源极线段进行解码，以及从特定单元的行地址生成的存储体选择信号。 本地下拉电路设置有每个存储体，用于在开始存储器访问操作时停用所选择的源线段。

公开(公告)号：US07093156B1

公开(公告)日：2006-08-15

申请号：US10144020

申请日：2002-05-13

Applicant: Alex Shubat ,  Randall Lee Reichenbach

Inventor： Alex Shubat ,  Randall Lee Reichenbach

IPC: G06F11/00

CPC classification number: G11C29/4401 ,  G11C29/16 ,  G11C29/48 ,  G11C29/785 ,  G11C29/802 ,  G11C2029/0401

Abstract: An embedded test and repair (ETR) scheme and interface for generating a self-test-and-repair (STAR) memory device using an integrated design environment. User interface and supporting program code is operable to provide a dialog box for defining a memory group that includes one or more memory instances, each having corresponding fuse element requirements based on its configuration data. BIST elements and a processor compiler for providing ETR functionality are also specified via suitable portions of the integrated GUI. A fuse equation is employed for computing the number of fuses for each memory instance, which equation is derived based on the memory configuration. Fuse information for each memory instance is automatically passed to a fuse compiler that generates a fuse box having an appropriate number of fuses that can accommodate the fuse requirements of the memory instances of the group.

Abstract translation: 嵌入式测试和修复（ETR）方案和接口，用于使用集成设计环境生成自检和维修（STAR）存储器设备。 用户界面和支持程序代码可操作以提供用于定义包括一个或多个存储器实例的存储器组的对话框，每个存储器实例基于其配置数据具有对应的熔丝元件要求。 BIST元件和用于提供ETR功能的处理器编译器也通过集成GUI的适当部分来指定。 采用熔丝方程来计算每个存储器实例的保险丝数量，该方程式基于存储器配置导出。 每个存储器实例的保险丝信息被自动传递到保险丝编译器，该保险丝编译器产生具有适当数量的保险丝的保险丝盒，该保险丝盒可以适应该组的存储器实例的保险丝要求。

公开(公告)号：US07061794B1

公开(公告)日：2006-06-13

申请号：US10813419

申请日：2004-03-30

Applicant: Deepak Sabharwal ,  Alexander Shubat

Inventor： Deepak Sabharwal ,  Alexander Shubat

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C11/417

Abstract: A source-biasing mechanism for leakage reduction in SRAM. In standby mode, wordlines are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a selected wordline deactivates the source-biasing potential provided to the selected row of SRAM cells, whereas the remaining SRAM cells on the selected bitline column continue to be source-biased.

Abstract translation: 用于SRAM中泄漏减少的源偏置机制。 在待机模式下，取消选择字线，并向SRAM单元提供源极偏置电位。 在读取模式下，所选择的字线禁止提供给所选择的SRAM单元行的源极偏置电位，而所选位线列上的剩余SRAM单元继续源偏置。