Semiconductor device including bit line formed using damascene technique and method of fabricating the same

Invention Grant

US07098135B2 Semiconductor device including bit line formed using damascene technique and method of fabricating the same 有权

Title translation: 包括使用镶嵌技术形成的位线的半导体器件及其制造方法

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Patent Title: Semiconductor device including bit line formed using damascene technique and method of fabricating the same
Patent Title (中): 包括使用镶嵌技术形成的位线的半导体器件及其制造方法
Application No.: US10703328

Application Date: 2003-11-07
Publication No.: US07098135B2

Publication Date: 2006-08-29
Inventor: Seung-pil Chung , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi , Seung-young Son , Sang-yong Kim
Applicant: Seung-pil Chung , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi , Seung-young Son , Sang-yong Kim
Applicant Address: KR Kyungki-Do
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR Kyungki-Do
Agency: F. Chau & Associates, LLC
Priority: KR10-2003-0002421 20030114
Main IPC: H01L21/311
IPC: H01L21/311

Semiconductor device including bit line formed using damascene technique and method of fabricating the same

Abstract:

A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.

Abstract(Chinese):

一种包括使用镶嵌技术形成的位线的半导体器件及其制造方法。该方法包括在基板上形成绝缘层，通过将绝缘层蚀刻到局部深度形成沟槽，并在槽的内壁上形成间隔物。通过使用间隔物作为蚀刻掩模蚀刻设置在凹槽下方的绝缘层来形成开口。形成导电层以填充开口。形成覆盖层以填充凹槽。

Public/Granted literature

US20040137743A1 Semiconductor device including bit line formed using damascene technique and method of fabricating the same Public/Granted day:2004-07-15

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/18	...器件有由周期表Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料
H01L21/30	....用H01L21/20至H01L21/26各组不包含的方法或设备处理半导体材料的（在半导体材料上制作电极的入H01L21/28）
H01L21/31	.....在半导体材料上形成绝缘层的，例如用于掩膜的或应用光刻技术的（密封层入H01L21/56）；以及这些层的后处理；这些层的材料的选择
H01L21/3105	......后处理
H01L21/311	.......绝缘层的刻蚀