Invention Grant
- Patent Title: Etching process to avoid polysilicon notching
- Patent Title (中): 蚀刻工艺避免多晶硅切口
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Application No.: US11033912Application Date: 2005-01-11
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Publication No.: US07109085B2Publication Date: 2006-09-19
- Inventor: Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
- Applicant: Shiang-Bau Wang , Li-Te Lin , Ming-Ching Chang , Ryan Chia-Jen Chen , Yuan-Hung Chiu , Hun-Jan Tao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Tung & Associates
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
A method for plasma assisted etching of a polysilicon containing gate electrode to reduce or avoid polysilicon notching at a base portion including providing a semiconducting substrate; forming a gate dielectric layer on the semiconducting substrate; forming a polysilicon layer on the gate dielectric; patterning a photoresist layer over the polysilicon layer for etching a gate electrode; carrying out a first plasma assisted etch process to etch through a major thickness portion of the polysilicon layer; carrying out a first inert gas plasma treatment; carrying out a second plasma assisted etch process to include exposing portions of the underlying gate dielectric layer; carrying out a second inert gas plasma treatment; and, carrying out a third plasma assisted etch process to fully expose the underlying gate dielectric layer adjacent either side of the gate electrodes.
Public/Granted literature
- US20060154487A1 ETCHING PROCESS TO AVOID POLYSILICON NOTCHING Public/Granted day:2006-07-13
Information query
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