Invention Grant
- Patent Title: Semiconductor device and method of manufacturing same
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Application No.: US10866701Application Date: 2004-06-15
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Publication No.: US07109553B2Publication Date: 2006-09-19
- Inventor: Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
- Applicant: Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- Priority: JP2001-216428 20010717; JP2001-299863 20010928
- Main IPC: H01L29/76
- IPC: H01L29/76

Abstract:
A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
Public/Granted literature
- US20040222465A1 Semiconductor device and method of manufacturing same Public/Granted day:2004-11-11
Information query
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