发明授权
- 专利标题： Semiconductor device including a capacitance
- 专利标题（中）： 包括电容的半导体装置
-
申请号： US10995193申请日： 2004-11-24
-
公开(公告)号： US07112835B2公开(公告)日： 2006-09-26
- 发明人: Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
- 申请人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权： JP2001-284866 20010919
- 主分类号： H01L29/93
- IPC分类号： H01L29/93
摘要：
It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).
公开/授权文献
- US20050087779A1 Semiconductor device including a capacitance 公开/授权日：2005-04-28
信息查询
IPC分类:
