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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20090047757A1

    公开(公告)日：2009-02-19

    申请号：US12253510

    申请日：2008-10-17

    申请人： Mikio TSUJIUCHI ,  Toshiaki IWAMATSU ,  Takashi IPPOSHI

    发明人： Mikio TSUJIUCHI ,  Toshiaki IWAMATSU ,  Takashi IPPOSHI

    IPC分类号： H01L21/336

    CPC分类号： H01L29/458 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

    摘要： In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

    摘要翻译： 在SOI衬底中形成的元件之间的隔离部分沟槽隔离的半导体器件中，针对晶体管的源极漏极的电阻降低和泄漏电流的降低。 在形成在掩埋氧化膜层（BOX层）上的SOI层中的隔离绝缘层规定的有源区域中形成MOS晶体管。 隔离绝缘层是尚未到达BOX层的部分沟槽隔离，源区和漏区包括彼此相互质量数不同的第一和第二杂质离子。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20080203479A1

    公开(公告)日：2008-08-28

    申请号：US12108369

    申请日：2008-04-23

    申请人： Tetsuya WATANABE ,  Takashi IPPOSHI

    发明人： Tetsuya WATANABE ,  Takashi IPPOSHI

    IPC分类号： H01L29/786

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78615

    摘要： In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.

    摘要翻译： 在PMOS晶体管中，源极 - 漏极区域沿着栅极宽度分成四个部分，并且具有四个独立源极区域和四个独立漏极区域的布置的布置。 部分沟槽隔离绝缘膜被布置成与四个源极区域之间的整个相对表面接触，使得形成在栅电极下方的沟道区域跨越沟道长度被划分。 包含浓度相对较高的N型杂质的身体绑扎区域与源极区域与栅电极相对的侧表面接触，并且身体区域的电位通过身体连接的孔区域固定 地区。

    SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20070221995A1

    公开(公告)日：2007-09-27

    申请号：US11672487

    申请日：2007-02-07

    申请人： Takaya SUZUKI ,  Takashi IPPOSHI

    发明人： Takaya SUZUKI ,  Takashi IPPOSHI

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.

    摘要翻译： 本发明实现了半导体器件的小型化。 在第一绝缘膜上形成围绕半导体层的岛状半导体层和第二绝缘膜，并且由导电膜形成的电阻元件（例如，多晶硅电阻元件）被布置成重叠 到半导体层的上表面。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20070105329A1

    公开(公告)日：2007-05-10

    申请号：US11617936

    申请日：2006-12-29

    申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

    发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

    IPC分类号： H01L29/76 ,  H01L21/8222

    CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

    摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。

    Semiconductor device for limiting leakage current
    9.
    发明申请
    Semiconductor device for limiting leakage current 失效

    公开(公告)号：US20060244064A1

    公开(公告)日：2006-11-02

    申请号：US11448827

    申请日：2006-06-08

    申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu

    发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu

    IPC分类号： H01L27/12

    CPC分类号： H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

    摘要： Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).