- Patent Title: Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
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Application No.: US11036961Application Date: 2005-01-14
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Publication No.: US07120064B2Publication Date: 2006-10-10
- Inventor: Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
- Applicant: Peter W. Lee , Fu-Chang Hsu , Hsing-Ya Tsao , Han-Rei Ma , Koucheng Wu
- Applicant Address: US CA San Jose
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Rosemary L. S. Pike
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.
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