Invention Grant
- Patent Title: Methods for selective deposition to improve selectivity
-
Application No.: US10744195Application Date: 2003-12-22
-
Publication No.: US07129139B2Publication Date: 2006-10-31
- Inventor: Anand Murthy , Nayanee Gupta , Chris Auth , Glenn A. Glass
- Applicant: Anand Murthy , Nayanee Gupta , Chris Auth , Glenn A. Glass
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kathy J. Ortiz
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.
Public/Granted literature
- US20050133832A1 Methods for selective deposition to improve selectivity Public/Granted day:2005-06-23
Information query
IPC分类: