公开(公告)号：US20060057809A1

公开(公告)日：2006-03-16

申请号：US11270933

申请日：2005-11-10

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US20050133832A1

公开(公告)日：2005-06-23

申请号：US10744195

申请日：2003-12-22

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

公开(公告)号：US20050230760A1

公开(公告)日：2005-10-20

申请号：US11152266

申请日：2005-06-13

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/76

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US07358547B2

公开(公告)日：2008-04-15

申请号：US11152266

申请日：2005-06-13

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

IPC: H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

公开(公告)号：US07129139B2

公开(公告)日：2006-10-31

申请号：US10744195

申请日：2003-12-22

Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn A. Glass

IPC: H01L21/8234

CPC classification number: H01L29/66636 ,  H01L21/823418

Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.