Invention Grant
US07129761B2 Digital delay-locked loop circuits with hierarchical delay adjustment
有权
具有分层延迟调整的数字延迟锁定环路
- Patent Title: Digital delay-locked loop circuits with hierarchical delay adjustment
- Patent Title (中): 具有分层延迟调整的数字延迟锁定环路
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Application No.: US11256215Application Date: 2005-10-21
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Publication No.: US07129761B2Publication Date: 2006-10-31
- Inventor: Seong-Hoon Lee
- Applicant: Seong-Hoon Lee
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fish & Neave IP Group Ropes & Gray LLP
- Main IPC: H03L7/06
- IPC: H03L7/06

Abstract:
Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.
Public/Granted literature
- US20060071696A1 Digital delay-locked loop circuits with hierarchical delay adjustment Public/Granted day:2006-04-06
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