Invention Grant
US07161823B2 Semiconductor memory device and method of arranging signal and power lines thereof 有权
半导体存储器件及其信号和电源线的布置方法

Semiconductor memory device and method of arranging signal and power lines thereof
Abstract:
Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.
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