Invention Grant
US07161823B2 Semiconductor memory device and method of arranging signal and power lines thereof
有权
半导体存储器件及其信号和电源线的布置方法
- Patent Title: Semiconductor memory device and method of arranging signal and power lines thereof
- Patent Title (中): 半导体存储器件及其信号和电源线的布置方法
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Application No.: US11134855Application Date: 2005-05-19
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Publication No.: US07161823B2Publication Date: 2007-01-09
- Inventor: Jae-Young Lee , Joon-Hyuk Kwon , Chi-Wook Kim , Sung-Hoon Kim , Youn-Sik Park
- Applicant: Jae-Young Lee , Joon-Hyuk Kwon , Chi-Wook Kim , Sung-Hoon Kim , Youn-Sik Park
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Marger Johnson & McCollom, P.C.
- Priority: KR10-2004-0040542 20040603; KR10-2004-0074730 20040917
- Main IPC: G11C5/06
- IPC: G11C5/06

Abstract:
Method and apparatus for use, e.g., with Synchronous Dynamic Random Access Memory (SDRAM) circuits are disclosed. In one described embodiment, three metal layers are deposited and patterned in turn overlying a memory array portion of an SDRAM. Relatively wide power conductors are routed on a third metal layer, allowing power conductors to be reduced in size, or in some cases eliminated, on first and second metal layers. The relatively wide power conductors thus can provide a more stable power supply to the memory array, and also free some space on first and/or second metal for routing of additional and/or more widely spaced signal conductors. Other embodiments are described and claimed.
Public/Granted literature
- US20050286285A1 Semiconductor memory device and method of arranging signal and power lines thereof Public/Granted day:2005-12-29
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