公开(公告)号：US08708172B2

公开(公告)日：2014-04-29

申请号：US12969775

申请日：2010-12-16

申请人： Kyung-Soo Kim ,  Hanjong Ju ,  Soo Hyun Kim ,  In Gwun Jang ,  Yunsub Jung ,  Eun Ho Kim ,  Youn Sik Park ,  Byung Man Kwak

发明人： Kyung-Soo Kim ,  Hanjong Ju ,  Soo Hyun Kim ,  In Gwun Jang ,  Yunsub Jung ,  Eun Ho Kim ,  Youn Sik Park ,  Byung Man Kwak

IPC分类号： B66C19/00

CPC分类号： B66C19/002

摘要： A crane for loading and unloading a cargo includes multi-stage trolley. The multi-stage trolley for a crane includes a first trolley movable in a longitudinal direction along a boom of the crane; a second trolley movable in a lateral direction on the first trolley; a hoisting wire provided in the longitudinal direction along the boom; a spreader connected to the hoisting wire through the first trolley and the second trolley and supported by the hoisting wire, the spreader being movable in a vertical direction according to a movement of the hoisting wire. The multi-stage trolley further includes a sheave block unit for changing a direction of the hoisting wire to maintain a vertical level of the spreader constant when the first trolley and/or the second trolley is moved.

摘要翻译： 装载货物的起重机包括多级手推车。 起重机的多级手推车包括沿起重机的起重臂沿长度方向移动的第一台车; 在第一台车上沿横向移动的第二台车; 沿着所述起重臂沿长度方向设置的起吊线; 通过第一手推车和第二手推车连接到起吊线并由提升线支撑的吊具，吊具可根据吊装线的移动在垂直方向上移动。 多级手推车还包括滑轮组件单元，用于当第一手推车和/或第二手推车移动时，改变吊装线的方向以保持吊具的垂直水平恒定。

公开(公告)号：US20110247991A1

公开(公告)日：2011-10-13

申请号：US12969775

申请日：2010-12-16

申请人： Kyung-Soo KIM ,  Hanjong Ju ,  Soo Hyun Kim ,  In Gwun Jang ,  Yunsub Jung ,  Eun Ho Kim ,  Youn Sik Park ,  Byung Man Kwak

发明人： Kyung-Soo KIM ,  Hanjong Ju ,  Soo Hyun Kim ,  In Gwun Jang ,  Yunsub Jung ,  Eun Ho Kim ,  Youn Sik Park ,  Byung Man Kwak

IPC分类号： B66C11/20

CPC分类号： B66C19/002

摘要： A crane for loading and unloading a cargo includes multi-stage trolley. The multi-stage trolley for a crane includes a first trolley movable in a longitudinal direction along a boom of the crane; a second trolley movable in a lateral direction on the first trolley; a hoisting wire provided in the longitudinal direction along the boom; spreader connected to the hoisting wire through the first trolley and the second trolley and supported by the hoisting wire, the spreader being movable in a vertical direction according to a movement of the hoisting wire. The multi-stage trolley further includes a sheave block unit for changing a direction of the hoisting wire to maintain a vertical level of the spreader constant when the first trolley and/or the second trolley is moved.

摘要翻译： 装载货物的起重机包括多级手推车。 起重机的多级手推车包括沿起重机的起重臂沿长度方向移动的第一台车; 在第一台车上沿横向移动的第二台车; 沿着所述起重臂沿长度方向设置的起吊线; 吊具通过第一手推车和第二手推车连接到提升线上并由提升线支撑，吊具可根据吊装线的移动在垂直方向上移动。 多级手推车还包括滑轮组件单元，用于当第一手推车和/或第二手推车移动时，改变吊装线的方向以保持吊具的垂直水平恒定。

公开(公告)号：US20110208988A1

公开(公告)日：2011-08-25

申请号：US13064961

申请日：2011-04-28

申请人： Hyun-Jin Kim ,  Ho-young Song ,  Seong-Jin Jang ,  Youn-sik Park

发明人： Hyun-Jin Kim ,  Ho-young Song ,  Seong-Jin Jang ,  Youn-sik Park

IPC分类号： G06F1/04

CPC分类号： G11C7/22 ,  G11C7/222

摘要： A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.

摘要翻译： 提供了一种等待时间信号发生器及其方法。 示例性延迟信号发生器可以包括采样时钟信号发生器，其基于所接收的时钟信号来调整多个初始采样时钟信号，以产生多个经调整的采样时钟信号;锁存使能信号供应单元，调整多个初始锁存使能信号 基于所述多个初始采样时钟信号中的给定一个以产生多个调整的锁存使能信号，以及包括多个延迟锁存器的锁存单元，所述多个延迟锁存器中的每一个基于一个等待锁存器选择性地锁存给定的内部读取命令 多个经调整的采样时钟信号中的一个和多个调整的锁存使能信号中的一个。

公开(公告)号：US07679985B2

公开(公告)日：2010-03-16

申请号：US11863141

申请日：2007-09-27

申请人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

发明人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

摘要翻译： 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US20080094932A1

公开(公告)日：2008-04-24

申请号：US11702569

申请日：2007-02-06

申请人： Min-Sang Park ,  Jeong-Don Lim ,  Youn-Sik Park

发明人： Min-Sang Park ,  Jeong-Don Lim ,  Youn-Sik Park

IPC分类号： G11C8/18 ,  G11C29/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/20 ,  G11C2029/3602 ,  G11C2207/2245

摘要： A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles. An example method may for achieving an single pumped address (SPA) mode in a semiconductor memory device configured for a double pumped address (DPA) mode may include receiving a first external address, generating a first internal address corresponding to the received first external address, receiving a second external address, generating a second internal address corresponding to the received second external address and delaying the generation of the first internal address to reduce a clock cycle interval between the generated first and second internal addresses.

摘要翻译： 提供半导体存储器件及其方法。 示例性半导体存储器件可以包括在正常操作期间根据第一寻址协议操作并且在测试操作期间根据第二寻址协议操作的内部地址产生电路，与第一数量的时钟周期相关联的第一寻址协议用于 传送存储器地址和与第二数量的时钟周期相关联的用于传送存储器地址的第二寻址协议，第一数量的时钟周期大于第二数量的时钟周期。 在针对双抽取地址（DPA）模式配置的半导体存储器件中实现单个泵浦地址（SPA）模式的示例性方法可包括：接收第一外部地址，产生对应于所接收的第一外部地址的第一内部地址， 接收第二外部地址，产生对应于所接收的第二外部地址的第二内部地址，并延迟第一内部地址的产生，以减小所生成的第一和第二内部地址之间的时钟周期间隔。

公开(公告)号：US20080056057A1

公开(公告)日：2008-03-06

申请号：US11850754

申请日：2007-09-06

申请人： Hyun-jin KIM ,  Ho-young SONG ,  Youn-sik PARK ,  Seong-jin JANG

发明人： Hyun-jin KIM ,  Ho-young SONG ,  Youn-sik PARK ,  Seong-jin JANG

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1057 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

摘要： A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing an internal clock signal by n, first and second sampling signals obtained by delaying the internal clock signal, a first output control clock signal obtained by dividing the internal clock signal by n, and a column address strobe (CAS) latency signal. The synchronous semiconductor memory device also includes a data output buffer, which outputs data by buffering internal data in response to the output control signal and the first output control clock signal.

摘要翻译： 一个同步半导体存储器件包括一个输出控制信号发生器，它产生一个输出控制信号，该输出控制信号对应于通过将内部时钟信号除以n而获得的延迟内部时钟信号延迟读取信息信号获得的信号，第一和第二 通过延迟内部时钟信号获得的采样信号，通过将内部时钟信号除以n获得的第一输​​出控制时钟信号和列地址选通（CAS）等待时间信号。 同步半导体存储器件还包括数据输出缓冲器，其通过响应于输出控制信号和第一输出控制时钟信号缓冲内部数据而输出数据。

公开(公告)号：US07295454B2

公开(公告)日：2007-11-13

申请号：US11225221

申请日：2005-09-12

申请人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

发明人： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

IPC分类号： G11C5/06

CPC分类号： H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

摘要翻译： 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US07268579B2

公开(公告)日：2007-09-11

申请号：US11030302

申请日：2005-01-07

申请人： Youn-Sik Park

发明人： Youn-Sik Park

IPC分类号： H03K17/16

CPC分类号： H04L25/028 ,  H04L25/0278

摘要： A semiconductor integrated circuit includes at least one pad coupled to at least one bus line, the at least one pad having a first side, a second side, a third side, and a fourth side; a transmitter for transmitting a signal from an internal circuit externally via the at least one pad; and a termination circuit for terminating the at least one bus line. Either one of the transmitter and the termination circuit is disposed to face the first and second sides of the at least one pad and the other of the transmitter and the termination circuit is disposed to either one of the third and fourth sides of the at least one pad.

摘要翻译： 半导体集成电路包括耦合到至少一个总线的至少一个焊盘，所述至少一个焊盘具有第一侧，第二侧，第三侧和第四侧; 发送器，用于经由所述至少一个衬垫从外部发送来自内部电路的信号; 以及用于终止所述至少一条总线线路的终端电路。 发射机和终端电路中的任何一个设置成面对至少一个焊盘的第一和第二侧，并且发射器和终端电路中的另一个设置在至少一个焊盘的第三和第四侧中的任一个上 垫。

公开(公告)号：US07853840B2

公开(公告)日：2010-12-14

申请号：US11702569

申请日：2007-02-06

申请人： Min-Sang Park ,  Jeong-Don Lim ,  Youn-Sik Park

发明人： Min-Sang Park ,  Jeong-Don Lim ,  Youn-Sik Park

IPC分类号： G11C29/00 ,  G01R31/28 ,  G01R31/26 ,  G06F17/50

CPC分类号： G11C7/1039 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/20 ,  G11C2029/3602 ,  G11C2207/2245

摘要： A semiconductor memory device and methods thereof are provided. The example semiconductor memory device may include an internal address generating circuit operating in accordance with a first addressing protocol during normal operation and operating in accordance with a second addressing protocol during a test operation, the first addressing protocol associated with a first number of clock cycles for transferring a memory address and the second addressing protocol associated with a second number of clock cycles for transferring a memory address, the first number of clock cycles being greater than the second number of clock cycles. An example method may for achieving an single pumped address (SPA) mode in a semiconductor memory device configured for a double pumped address (DPA) mode may include receiving a first external address, generating a first internal address corresponding to the received first external address, receiving a second external address, generating a second internal address corresponding to the received second external address and delaying the generation of the first internal address to reduce a clock cycle interval between the generated first and second internal addresses.

摘要翻译： 提供半导体存储器件及其方法。 示例性半导体存储器件可以包括在正常操作期间根据第一寻址协议操作并且在测试操作期间根据第二寻址协议操作的内部地址产生电路，与第一数量的时钟周期相关联的第一寻址协议用于 传送存储器地址和与第二数量的时钟周期相关联的用于传送存储器地址的第二寻址协议，第一数量的时钟周期大于第二数量的时钟周期。 在针对双抽取地址（DPA）模式配置的半导体存储器件中实现单个泵浦地址（SPA）模式的示例性方法可包括：接收第一外部地址，产生对应于所接收的第一外部地址的第一内部地址， 接收第二外部地址，产生对应于所接收的第二外部地址的第二内部地址，并延迟第一内部地址的产生，以减小所生成的第一和第二内部地址之间的时钟周期间隔。

公开(公告)号：US07633329B2

公开(公告)日：2009-12-15

申请号：US12107690

申请日：2008-04-22

申请人： Youn-Sik Park

发明人： Youn-Sik Park

IPC分类号： H03K17/00

CPC分类号： H03K19/018528 ,  H03K5/1515

摘要： In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal. The single signal-to-differential signal converter further includes a second differential signal generating portion for generating a second signal and an inverted second signal which have the opposite phases to each other to the second and third nodes in response to the inverted single input signal, wherein the single signal-to-differential signal converter outputs differential signals such that the first and second signals applied to the second node are merged by a phase interpolation and the inverted first and second signals applied to the third node are merged by a phase interpolation.

摘要翻译： 在一个示例实施例中，单个信号至差分信号转换器包括第一逆变器，用于接收和反相单个输入信号并将反相的单个输入信号输出到第一节点;以及第一差分信号产生部分，用于产生第一信号 以及反向第一信号，其响应于单个输入信号而具有彼此相对于第二和第三节点的相位。 单个信号对差分信号转换器还包括第二差分信号产生部分，用于响应于反相的单个输入信号，产生具有相对于第二和第三节点的相反相位的第二信号和反相的第二信号， 其中单个信号对差分信号转换器输出差分信号，使得施加到第二个节点的第一和第二信号通过相位插值合并，并且施加到第三个节点的反相的第一和第二信号被相位插值合并。