发明授权
US07165169B2 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
有权
基于分支指令类型的辅助预测器具有选择性覆盖的推测分支目标地址缓存
- 专利标题: Speculative branch target address cache with selective override by secondary predictor based on branch instruction type
- 专利标题(中): 基于分支指令类型的辅助预测器具有选择性覆盖的推测分支目标地址缓存
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申请号: US09849799申请日: 2001-05-04
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公开(公告)号: US07165169B2公开(公告)日: 2007-01-16
- 发明人: G. Glenn Henry , Thomas C. McDonald
- 申请人: G. Glenn Henry , Thomas C. McDonald
- 申请人地址: US CA Fremont
- 专利权人: IP-First, LLC
- 当前专利权人: IP-First, LLC
- 当前专利权人地址: US CA Fremont
- 代理商 E. Alan Davis; James W. Huffman
- 主分类号: G06F9/26
- IPC分类号: G06F9/26
摘要:
A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target address cache in the primary branch predictor speculatively predicts a branch target address and direction based on an instruction cache fetch address prior to decoding the instruction, and the processor branches to the speculative target address if the speculative direction is predicted taken. Later in the pipeline, decode logic decodes the instruction and determines the branch instruction type, such as whether the branch instruction is a conditional branch, a return instruction, a program counter-relative type branch, an indirect branch, etc. Depending upon the branch type, if the primary and secondary predictions do not match, the processor branches based on the secondary prediction to override the branch taken based on the primary prediction.
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