公开(公告)号：US06823444B1

公开(公告)日：2004-11-23

申请号：US09898832

申请日：2001-07-03

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F938

CPC分类号： G06F9/3806 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/382

摘要： A branch control apparatus in a microprocessor. The branch control apparatus includes an instruction buffer having a plurality of stages that buffer cache lines of instruction bytes received from an instruction cache. A multiplexer selects one of the bottom three stages in the instruction buffer to provide to instruction format logic. The multiplexer selects a stage based on a branch indicator, an instruction wrap indicator, and a carry indicator. The branch indicator indicates whether the processor previously branched to a target address provided by a branch target address cache. The branch indicator and target address are previously stored in association with the stage containing the branch instruction for which the target address is cached. The wrap indicator indicates whether the currently formatted instruction wraps across two cache lines. The carry indicator indicates whether the current instruction being formatted occupies the last byte of the currently formatted instruction buffer stage.

摘要翻译： 微处理器中的分支控制装置。 分支控制装置包括具有缓冲从指令高速缓存接收的指令字节的高速缓存行的多个级的指令缓冲器。 多路复用器选择指令缓冲器中的三个底层之一来提供指令格式逻辑。 复用器基于分支指示符，指令换行指示符和进位指示器选择一个级。 分支指示符指示处理器是否先前分支到由分支目标地址高速缓存提供的目标地址。 分支指示符和目标地址预先与包含缓存目标地址的转移指令的级相关联地存储。 包装指示符指示当前格式化的指令是否包含在两条缓存行之间。 进位指示器指示当前正在格式化的指令是否占用当前格式化指令缓冲区的最后一个字节。

公开(公告)号：US07707397B2

公开(公告)日：2010-04-27

申请号：US11181210

申请日：2005-07-14

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F7/48 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3806 ,  G06F9/30058 ,  G06F9/3844

摘要： A branch prediction apparatus having two two-way set associative cache memories each indexed by a lower portion of an instruction cache fetch address is disclosed. The index selects a group of four entries, one from each way of each cache. Each entry stores a single target address of a different previously executed branch instruction. For some groups, the four entries cache target addresses for one branch instruction in each of four different cache lines, to obtain four-way group associativity; for other groups, the four entries cache target addresses for one branch instruction in each of two different cache lines and two branch instructions in a third different cache line, to effectively obtain three-way group associativity, depending on the distribution of the branch instructions in the program. The apparatus trades off associativity for number of predictable branches per cache line on an index-by-index basis to efficiently use storage space.

摘要翻译： 公开了一种分支预测装置，其具有由指令高速缓存取出地址的下部索引的两个双向组关联高速缓冲存储器。 索引选择一组四个条目，一个来自每个缓存的每个方式。 每个条目存储不同的先前执行的分支指令的单个目标地址。 对于一些组，四个条目在四个不同的高速缓存行中的每一个中缓存一个分支指令的目标地址，以获得四方组关联性; 对于其他组，四个条目在两个不同的高速缓存行中的每一个中的一个分支指令和第三个不同的高速缓存行中的两个分支指令中缓存目标地址，以根据分支指令的分布来有效地获得三方组关联性 该程序。 该装置在逐个索引的基础上交换每个缓存行的可预测分支的数量，以有效地使用存储空间。

公开(公告)号：US07159098B2

公开(公告)日：2007-01-02

申请号：US10920120

申请日：2004-08-17

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F9/38

CPC分类号： G06F9/3806 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/382

摘要： A branch control apparatus in a microprocessor. The branch control apparatus includes an instruction buffer having a plurality of stages that buffer cache lines of instruction bytes received from an instruction cache. A multiplexer selects one of the bottom three stages in the instruction buffer to provide to instruction format logic. The multiplexer selects a stage based on a branch indicator, an instruction wrap indicator, and a carry indicator. The branch indicator indicates whether the processor previously branched to a target address provided by a branch target address cache. The branch indicator and target address are previously stored in association with the stage containing the branch instruction for which the target address is cached. The wrap indicator indicates whether the currently formatted instruction wraps across two cache lines. The carry indicator indicates whether the current instruction being formatted occupies the last byte of the currently formatted instruction buffer stage.

摘要翻译： 微处理器中的分支控制装置。 分支控制装置包括具有缓冲从指令高速缓存接收的指令字节的高速缓存行的多个级的指令缓冲器。 多路复用器选择指令缓冲器中的三个底层之一来提供指令格式逻辑。 复用器基于分支指示符，指令换行指示符和进位指示器选择一个级。 分支指示符指示处理器是否先前分支到由分支目标地址高速缓存提供的目标地址。 分支指示符和目标地址预先与包含缓存目标地址的转移指令的级相关联地存储。 包装指示符指示当前格式化的指令是否包含在两条缓存行之间。 进位指示器指示当前正在格式化的指令是否占用当前格式化指令缓冲区的最后一个字节。

公开(公告)号：US07203824B2

公开(公告)日：2007-04-10

申请号：US09906381

申请日：2001-07-16

申请人： Brent Bean ,  G. Glenn Henry ,  Thomas C. McDonald

发明人： Brent Bean ,  G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F9/32

CPC分类号： G06F9/30149 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3867

摘要： A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

公开(公告)号：US07631172B2

公开(公告)日：2009-12-08

申请号：US11609261

申请日：2006-12-11

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/3861 ,  G06F9/3806 ,  G06F9/3848

摘要： A microprocessor for predicting return instruction target addresses is disclosed. A branch target address cache stores a plurality of target address predictions and a corresponding plurality of override indicators for a corresponding plurality of return instructions, and provides a prediction of the target address of the return instruction from the target address predictions and provides a corresponding override indicator from the override indicators. Each has a true value when the return stack has mispredicted the target address of the corresponding return instruction for a most recent execution of the return instruction. A return stack also provides a prediction of the target address of the return instruction. Branch control logic causes the microprocessor to branch to the prediction of the target address provided by the BTAC, and not to the prediction of the target address provided by the return stack, when the override indicator is a true value.

摘要翻译： 公开了一种用于预测返回指令目标地址的微处理器。 分支目标地址缓存存储多个目标地址预测和对应的多个返回指令的对应的多个覆盖指示符，并且从目标地址预测提供对返回指令的目标地址的预测，并提供相应的覆盖指示符 从覆盖指标。 当返回堆栈错误地预测了最近执行返回指令的相应返回指令的目标地址时，每个值都具有真实值。 返回栈还提供了返回指令的目标地址的预测。 分支控制逻辑使得微处理器转移到由BTAC提供的目标地址的预测，而不是当覆盖指示符是真值时对由返回栈提供的目标地址的预测。

公开(公告)号：US07200740B2

公开(公告)日：2007-04-03

申请号：US09849822

申请日：2001-05-04

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F9/30

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/3844 ,  G06F9/3861

摘要： A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branch target address cache (BTAC) of an instruction cache fetch address prior to decoding of the instruction to know whether it is actually a return instruction. The speculative return address is one of multiple return addresses simultaneously stored in the first call/return stack each pushed thereupon in response to the BTAC indicating a call instruction was fetched and prior to decoding the call instruction. The speculative return address is provided early in the pipeline and the microprocessor speculatively branches to the speculative return address. Later in the pipeline, a second call/return stack provides a non-speculative return address after the instruction is decoded and verified to be a return instruction. A comparator compares the speculative and non-speculative return addresses, and if the two addresses mismatch, the microprocessor branches to the non-speculative return address.

摘要翻译： 一种分支预测装置，其采用双重呼叫/返回栈来预测微处理器中的返回地址。 该装置包括第一呼叫/返回栈，其基于指令高速缓存提取地址的推测性分支目标地址高速缓存（BTAC）中的返回指令命令提供推测返回地址，在解码指令之前是否实际上是 返回指令。 推测返回地址是同时存储在第一个调用/返回栈中的多个返回地址之一，每个返回栈中的每一个被响应于BTAC指示已经取出了一个调用指令并在解码该调用指令之前被推送。 投机回报地址在管道早期提供，微处理器推测性地分支到投机回报地址。 在管道中，第二个调用/返回栈在指令被解码并被验证为返回指令之后提供非推测返回地址。 比较器比较推测和非推测返回地址，如果两个地址不匹配，则微处理器分支到非推测返回地址。

公开(公告)号：US07134005B2

公开(公告)日：2006-11-07

申请号：US09849658

申请日：2001-05-04

申请人： G. Glenn Henry ,  Thomas C. McDonald ,  Terry Parks

发明人： G. Glenn Henry ,  Thomas C. McDonald ,  Terry Parks

IPC分类号： G06F15/00

CPC分类号： G06F9/3865 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/3844

摘要： A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and is present in a cache line of instruction bytes provided by an instruction cache in response to a fetch address, a target address of the branch instruction, and a location of an opcode byte of the branch instruction within the cache line. The instruction cache provides the cache line to an instruction buffer and the BTAC provides the prediction, the target address, and the location in response to the fetch address. The microprocessor branches to the target address. A byte in the cache line within the instruction buffer indicated by the location provided by the BTAC is marked. An instruction decoder formats the instruction bytes in the cache line. The microprocessor erroneously branched to the target address if the instruction decoder indicates the marked byte is in a non-opcode location within one of the formatted instructions.

摘要翻译： 对于多个先前执行的分支指令中的每一个，微处理器缓存在分支目标地址高速缓存（BTAC）中：预测分支指令是否将被采用并且存在于由指令高速缓存提供的指令字节的高速缓存行中 响应于获取地址，分支指令的目标地址以及高速缓存行内的分支指令的操作码字节的位置。 指令高速缓存将缓存行提供给指令缓冲器，并且BTAC响应于提取地址提供预测，目标地址和位置。 微处理器分支到目标地址。 在由BTAC提供的位置指示的指令缓冲区内的高速缓存行中的一个字节被标记。 指令解码器格式化高速缓存行中的指令字节。 如果指令解码器指示标记字节在格式化指令之一内的非操作码位置，则微处理器错误地分支到目标地址。

公开(公告)号：US06886093B2

公开(公告)日：2005-04-26

申请号：US09849734

申请日：2001-05-04

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F9/38

CPC分类号： G06F9/30149 ,  G06F9/30054 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/3848

摘要： An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTAC is accessed in parallel with the instruction cache access, such that the direction prediction is provided before the actual instruction is decoded which is presumed to be a branch instruction corresponding to the direction prediction stored in the BTAC. In parallel with the BTAC access, a branch history table (BHT) is accessed to provide a second speculative direction prediction. The BHT is indexed with a gshare function of the instruction cache fetch address and a global branch history stored in a global branch history register. The BTAC also provides a selector that selects between the two speculative direction predictions.

摘要翻译： 一种用于以混合方式推测性地预测流水线微处理器中的分支指令的方向的装置。 分支目标地址缓存（BTAC）存储关于执行的分支指令的方向预测。 BTAC由指令缓存提取地址索引。 与指令高速缓存访​​问并行地访问BTAC，使得在被假定为与存储在BTAC中的方向预测相对应的分支指令的实际指令被解码之前提供方向预测。 与BTAC访问并行，访问分支历史表（BHT）以提供第二推测方向预测。 BHT用指令高速缓存提取地址的gshare函数和存储在全局分支历史寄存器中的全局分支历史进行索引。 BTAC还提供了一个选择器，可在两个推测方向预测之间进行选择。

公开(公告)号：US07234045B2

公开(公告)日：2007-06-19

申请号：US11208302

申请日：2005-08-19

申请人： G. Glenn Henry ,  Brent Bean ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Brent Bean ,  Thomas C. McDonald

IPC分类号： G06F9/32

CPC分类号： G06F9/3804 ,  G06F9/3806

摘要： A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing the first part of the branch instruction hits in the BTAC, the BTAC outputs a target address of the branch instruction and indicates the wrap condition. The target address is stored in a register. The next sequential fetch address selects a second cache line containing the second part of the branch instruction. After the two cache lines containing the branch instruction are fetched, the target address from the register is provided to the instruction cache in order to fetch a third cache line containing a target instruction of the branch. The three cache lines are stored in order in an instruction buffer for decoding.

摘要翻译： 微处理器中的分支控制装置。 该装置包括分支目标地址高速缓存（BTAC），其缓存分支指令是否跨越两个高速缓存线路的指示。 当包含分支指令的第一部分的第一高速缓存线的指令高速缓冲存取器地址在BTAC中命中时，BTAC输出转移指令的目标地址并指示换行条件。 目标地址存储在寄存器中。 下一个顺序取出地址选择包含分支指令第二部分的第二个高速缓存行。 在取出包含分支指令的两条高速缓存行之后，将来自寄存器的目标地址提供给指令高速缓存，以便获取包含该分支的目标指令的第三高速缓存行。 三条缓存行按顺序存储在用于解码的指令缓冲器中。

公开(公告)号：US07165169B2

公开(公告)日：2007-01-16

申请号：US09849799

申请日：2001-05-04

申请人： G. Glenn Henry ,  Thomas C. McDonald

发明人： G. Glenn Henry ,  Thomas C. McDonald

IPC分类号： G06F9/26

CPC分类号： G06F9/3842 ,  G06F9/3848

摘要： A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target address cache in the primary branch predictor speculatively predicts a branch target address and direction based on an instruction cache fetch address prior to decoding the instruction, and the processor branches to the speculative target address if the speculative direction is predicted taken. Later in the pipeline, decode logic decodes the instruction and determines the branch instruction type, such as whether the branch instruction is a conditional branch, a return instruction, a program counter-relative type branch, an indirect branch, etc. Depending upon the branch type, if the primary and secondary predictions do not match, the processor branches based on the secondary prediction to override the branch taken based on the primary prediction.

摘要翻译： 一种分支预测装置，具有主预测器和辅预测器，其基于解码的分支指令的类型选择性地覆盖主预测器。 主分支预测器中的分支目标地址高速缓存基于指令的解码之前的指令高速缓冲存取器地址推测性地预测分支目标地址和方向，并且如果预测了推测方向，则处理器分支到推测目标地址。 在流水线中，解码逻辑解码指令并确定分支指令类型，例如分支指令是条件分支，返回指令，程序反相对分支，间接分支等。根据分支 类型，如果主和次级预测不匹配，则处理器基于次级预测分支以覆盖基于主预测所取得的分支。