Invention Grant
- Patent Title: Dual damascene trench formation to avoid low-K dielectric damage
- Patent Title (中): 双镶嵌沟槽形成，以避免低K介电损伤
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Application No.: US10882058Application Date: 2004-06-30
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Publication No.: US07169701B2Publication Date: 2007-01-30
- Inventor: Chen-Nan Yeh , Tsiao-Chen Wu , Chao-Cheng Chen
- Applicant: Chen-Nan Yeh , Tsiao-Chen Wu , Chao-Cheng Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Tung & Associates
- Main IPC: H01L21/4763
- IPC: H01L21/4763
Abstract:
A method for forming a dual damascene including providing a first dielectric insulating layer including a via opening; forming an organic dielectric layer over the first IMD layer to include filling the via opening; forming a hardmask layer over the organic dielectric layer; photolithographically patterning and dry etching the hardmask layer and organic dielectric layer to leave a dummy portion overlying the via opening; forming an oxide liner over the dummy portion; forming a second dielectric insulating layer over the oxide liner to surround the dummy portion; planarizing the second dielectric insulating layer to expose the upper portion of the dummy portion; and, removing the organic dielectric layer to form a dual damascene opening including the oxide liner lining trench line portion sidewalls.
Public/Granted literature
- US20060003576A1 Dual damascene trench formation to avoid low-K dielectric damage Public/Granted day:2006-01-05
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