Invention Grant
- Patent Title: Semiconductor memory device capable of reducing power consumption during reading and standby
- Patent Title (中): 半导体存储器件能够在读取和待机期间降低功耗
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Application No.: US11304817Application Date: 2005-12-16
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Publication No.: US07170812B2Publication Date: 2007-01-30
- Inventor: Koji Nii
- Applicant: Koji Nii
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: McDermott Will & Emery LLP
- Priority: JP2003-279239 20030724
- Main IPC: G11C5/14
- IPC: G11C5/14
Abstract:
The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many “0”s. Therefore, the data of address 3 is inverted, and flag information “1” is written. The input data at addresses 1 and 2 includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.
Public/Granted literature
- US20060092746A1 Semiconductor memory device capable of reducing power consumption during reading and standby Public/Granted day:2006-05-04
Information query
