公开(公告)号：US10032781B2

公开(公告)日：2018-07-24

申请号：US14236067

申请日：2011-07-29

申请人： Koji Nii ,  Makoto Yabuuchi ,  Yasumasa Tsukamoto ,  Kengo Masuda

发明人： Koji Nii ,  Makoto Yabuuchi ,  Yasumasa Tsukamoto ,  Kengo Masuda

IPC分类号： H01L27/088 ,  H01L27/11 ,  H01L27/02 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  G11C11/412

摘要： In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

公开(公告)号：US08305836B2

公开(公告)日：2012-11-06

申请号：US13111422

申请日：2011-05-19

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C7/18 ,  G11C8/06 ,  G11C8/10 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104

摘要： First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns.

摘要翻译： 在由两个相邻行组成的每个集合中提供第一和第二读取字线。 在每列中提供第一，第二，第三和第四读取位线。 第一和第二读取字线中的每一个连接到相应的一组中的存储单元。 第一和第三读取位线中的每一个连接到每个组中的一行中的存储器单元，在相应的一列中的存储器单元中。 第二和第四读取位线中的每一个都连接到相应一个列中的存储器单元中的每个组中的另一行中的存储器单元。

公开(公告)号：US08238192B2

公开(公告)日：2012-08-07

申请号：US13026649

申请日：2011-02-14

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C8/00

CPC分类号： H01L27/0207 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11 ,  H01L27/1104

摘要： A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word line and second word line. Then, for example, when the same memory cell row is accessed, a voltage level of the power supply line is raised by a coupling capacitance of the word lines. Thus, even in identical-row-access, static noise margin in identical-row-access can be maintained to be as great as that in different-row-access. Therefore, for example, even when a size or the like of a driver transistor is not made larger, deterioration of static noise margin can be suppressed and a circuit area can be made smaller.

摘要翻译： 提供能够实现较小电路面积的多端口半导体存储器件。 提供存储单元的工作电压的电源线形成在形成字线的相同的金属互连层中，并且被设置在相邻的第一字线和第二字线之间。 然后，例如，当访问相同的存储单元行时，电源线的电压电平由字线的耦合电容升高。 因此，即使在相同行访问中，相同行访问中的静态噪声容限也可以保持与不同行访问中的一样大。 因此，例如，即使驱动晶体管的尺寸等不变大，也能够抑制静态噪声容限的劣化，能够使电路面积更小。

公开(公告)号：US08098533B2

公开(公告)日：2012-01-17

申请号：US12457936

申请日：2009-06-25

申请人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

摘要翻译： 针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。 该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。 电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。 在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。 因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

公开(公告)号：US20110221007A1

公开(公告)日：2011-09-15

申请号：US13110394

申请日：2011-05-18

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： H01L27/088

CPC分类号： G11C11/412 ,  G11C8/16 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104

摘要： In a multipart SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

摘要翻译： 在本发明的多部分SRAM存储单元中，第一端口的存取晶体管设置在p型阱中，并且第二端口的存取晶体管设置在p型阱中。 设置在存储单元中的所有晶体管的栅极沿相同的方向延伸。 通过该配置，可以获得具有在多端口SRAM存储单元或关联存储器中可以缩短位线的制造中的变化幅度增加的低功耗型SRAM存储单元的半导体存储器件。

公开(公告)号：US08018785B2

公开(公告)日：2011-09-13

申请号：US12909465

申请日：2010-10-21

申请人： Makoto Yabuuchi ,  Koji Nii

发明人： Makoto Yabuuchi ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

摘要翻译： 降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。 驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。 下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路 晶体管。 栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

公开(公告)号：US07602654B2

公开(公告)日：2009-10-13

申请号：US11889145

申请日：2007-08-09

申请人： Makoto Yabuuchi ,  Koji Nii

发明人： Makoto Yabuuchi ,  Koji Nii

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

摘要： A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

摘要翻译： 降低电源电压的驱动器电源电路被布置在字线驱动器的电源节点处。 驱动器电源电路包括N +掺杂多晶硅的非硅化物电阻元件和降低驱动器电源节点的电压电平的下拉电路。 下拉电路包括具有与下拉驱动器电源节点的电压电平的存储单元晶体管相同的阈值电压特性的下拉晶体管，以及至少调节下拉电路的栅极电压的栅极控制电路 晶体管。 栅极控制电路以与存储单元晶体管的阈值电压的变化相关联的方式校正下拉晶体管的栅极电位。

公开(公告)号：US07423916B2

公开(公告)日：2008-09-09

申请号：US11889393

申请日：2007-08-13

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/00

CPC分类号： G11C11/417 ,  G11C5/14 ,  G11C11/413

摘要： Level control signals are both set to H level, and potentials of power supply lines are both set to be lower than a power supply potential. In this manner, a gate leakage current during waiting and writing operation of a memory cell array can significantly be reduced. The level control signals are set to L level and H level respectively, and solely the potential of one of the power supply lines is set to be lower than the power supply potential. In this manner, power consumption during a reading operation of the memory cell array can be reduced.

摘要翻译： 电平控制信号都设置为H电平，电源线的电位都设置为低于电源电位。 以这种方式，可以显着地减少存储单元阵列的等待和写入操作期间的栅极泄漏电流。 电平控制信号分别设置为L电平和H电平，并且仅一个电源线的电位被设置为低于电源电位。 以这种方式，可以减少在存储单元阵列的读取操作期间的功耗。

公开(公告)号：US07376002B2

公开(公告)日：2008-05-20

申请号：US11384242

申请日：2006-03-21

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C8/16 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104

摘要： In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained.

摘要翻译： 在本发明的多端口SRAM存储单元中，第一端口的存取晶体管设置在p型阱中，第二端口的存取晶体管设置在p型阱中。 设置在存储单元中的所有晶体管的栅极沿相同的方向延伸。 通过该配置，可以获得具有在多端口SRAM存储单元或关联存储器中可以缩短位线的制造中的变化幅度增加的低功耗型SRAM存储单元的半导体存储器件。

公开(公告)号：US07170812B2

公开(公告)日：2007-01-30

申请号：US11304817

申请日：2005-12-16

申请人： Koji Nii

发明人： Koji Nii

IPC分类号： G11C5/14

CPC分类号： G11C11/417

摘要： The input data at address 0 is “00000000”, including many “0”s. The data at address 0 is inverted to “11111111”. At the same time, flag information “1” indicative of inversion is written into the flag bit of the same address 0. The input data at address 3 also includes many “0”s. Therefore, the data of address 3 is inverted, and flag information “1” is written. The input data at addresses 1 and 2 includes more “1”s than “0”s. Therefore, the data is not inverted, and flag information “0” is written. With regards to the written data, only the data at an address whose flag signal is “1” is inverted again in a reading mode to be eventually read out as a data output signal.

摘要翻译： 地址0的输入数据为“00000000”，包括许多“0”。 地址0的数据被反转为“11111111”。 同时，将表示反转的标志信息“1”写入相同地址0的标志位。 地址3处的输入数据也包括许多“0”。 因此，地址3的数据被反转，并且写入标志信息“1”。 地址1和2的输入数据比“0”更多的“1”。 因此，数据不反转，写入标志信息“0”。 关于写入数据，仅在标志信号为“1”的地址处的数据在读取模式下再次反相，最终作为数据输出信号被读出。