Invention Grant
- Patent Title: Method and apparatus for reducing electrical interconnection fatigue
- Patent Title (中): 减少电互连疲劳的方法和装置
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Application No.: US10322308Application Date: 2002-12-17
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Publication No.: US07173342B2Publication Date: 2007-02-06
- Inventor: Cheng Siew Tay , Swee Kian Cheng , Eng Huat Goh
- Applicant: Cheng Siew Tay , Swee Kian Cheng , Eng Huat Goh
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/485
- IPC: H01L23/485

Abstract:
A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
Public/Granted literature
- US20040113285A1 Method and apparatus for reducing electrical interconnection fatigue Public/Granted day:2004-06-17
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