发明授权
US07178046B2 Halting clock signals to input and result latches in processing path upon fetching of instruction not supported
有权
在不支持指令的提取时，将时钟信号停止到处理路径中的输入和结果锁存器
- 专利标题： Halting clock signals to input and result latches in processing path upon fetching of instruction not supported
- 专利标题（中）： 在不支持指令的提取时，将时钟信号停止到处理路径中的输入和结果锁存器
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申请号： US11095685申请日： 2005-04-01
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公开(公告)号： US07178046B2公开(公告)日： 2007-02-13
- 发明人: Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
- 申请人： Tetsuya Yamada , Tomoichi Hayashi , Sadaki Nakano , Takanobu Tsunoda , Osamu Nishii
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Antonelli, Terry, Stout and Kraus, LLP.
- 优先权： JP11-195409 19990709
- 主分类号： G06F1/32
- IPC分类号： G06F1/32 ; G06F9/30
摘要：
A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.
公开/授权文献
- US20050169086A1 Low power consumption microprocessor 公开/授权日：2005-08-04
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