Invention Grant
US07178115B2 Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing
失效
在ASIC / SOC制造中避免原型保持的制造方法和装置
- Patent Title: Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing
- Patent Title (中): 在ASIC / SOC制造中避免原型保持的制造方法和装置
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Application No.: US10412143Application Date: 2003-04-11
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Publication No.: US07178115B2Publication Date: 2007-02-13
- Inventor: Rochit Rajsuman , Hiroaki Yamoto
- Applicant: Rochit Rajsuman , Hiroaki Yamoto
- Applicant Address: JP Tokyo
- Assignee: Advantest Corp.
- Current Assignee: Advantest Corp.
- Current Assignee Address: JP Tokyo
- Agency: Muramatsu & Associates
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.
Public/Granted literature
- US20030217343A1 Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing Public/Granted day:2003-11-20
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