公开(公告)号：US07089135B2

公开(公告)日：2006-08-08

申请号：US10150777

申请日：2002-05-20

Applicant: Rochit Rajsuman ,  Shigeru Sugamori ,  Robert F. Sauer ,  Hiroaki Yamoto ,  James Alan Turnquist ,  Bruce R. Parnas ,  Anthony Le

Inventor： Rochit Rajsuman ,  Shigeru Sugamori ,  Robert F. Sauer ,  Hiroaki Yamoto ,  James Alan Turnquist ,  Bruce R. Parnas ,  Anthony Le

IPC: G01R31/00

CPC classification number: G01R31/31813 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/31917 ,  G01R31/31919 ,  G01R31/31928

Abstract: An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

Abstract translation: 一种基于事件的测试系统，用于测试在自动电子设计（EDA）环境下设计的待测IC器件（DUT）。 基于事件的测试系统包括事件存储器，用于存储在EDA环境中直接从对于期望的IC的设计数据的模拟得到的事件数据，其中表示每个事件的事件数据形成有指示来自预定点的时间长度的时间索引， 指示事件变化类型的事件类型，用于根据事件数据生成测试矢量的事件生成单元，其中由事件类型确定每个矢量的波形，并且通过累积波形的时间指数来确定波形的定时 以前的事件，以及用于向DUT提供测试向量并在预定定时评估DUT的响应输出的装置。

公开(公告)号：US06249889B1

公开(公告)日：2001-06-19

申请号：US09170179

申请日：1998-10-13

Applicant: Rochit Rajsuman ,  Hiroaki Yamoto

Inventor： Rochit Rajsuman ,  Hiroaki Yamoto

IPC: G11C2900

CPC classification number: G06F11/2236 ,  G06F11/263 ,  G11C29/36

Abstract: A method and structure for testing embedded memories in an integrated circuit chip having a microprocessor core therein. The method includes the steps of testing the microprocessor core by applying a test pattern and evaluating the resultant output of the microprocessor core, and confirming an integrity of the microprocessor core prior to testing the embedded memory, applying an object code of assembly language test program to the microprocessor core from a source external to the integrated circuit chip, generating a memory test pattern by the microprocessor core based on the object code of the assembly language test program, and applying the memory test pattern to the embedded memory and evaluating the resultant response of the memory by comparing the response with the expected data by the microprocessor core.

Abstract translation: 一种在其中具有微处理器核心的集成电路芯片中测试嵌入式存储器的方法和结构。 该方法包括以下步骤：通过应用测试图案和评估微处理器核心的合成输出来测试微处理器核心，并在测试嵌入式存储器之前确认微处理器核心的完整性，将汇编语言测试程序的目标代码应用于 所述微处理器核心从所述集成电路芯片外部的源起，基于所述汇编语言测试程序的目标代码产生由所述微处理器核心的存储器测试模式，以及将所述存储器测试模式应用于所述嵌入式存储器并评估所述微处理器核心的结果响应 通过将响应与微处理器核心的预期数据进行比较来记忆存储器。

公开(公告)号：US5867036A

公开(公告)日：1999-02-02

申请号：US655438

申请日：1996-05-29

Applicant: Rochit Rajsuman

Inventor： Rochit Rajsuman

IPC: G01R31/28 ,  G01R31/3185 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0944 ,  H03K19/096

CPC classification number: G01R31/318541

Abstract: Hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic include two registers that surround the Domino logic to allow that logic to be tested. One register receives an input test vector, loaded directly through a primary set of inputs or by a serial scan chain if the register inputs are not directly accessible. The second register latches the results of the test vector application. The register contents can either be read directly through a primary set of outputs if there is no static CMOS logic between the register outputs and a primary set of circuit outputs, or scanned out of the second register using a serial scan chain. Domino scan flip-flops, which reduce transistor count over conventional static scan flip-flops, can be used in the Domino logic as sequential elements to implement multiple logic functions. These scan flip-flops can be serially connected as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. Domino scan flip-flops allow all of the nominal logic to be tested in conjunction with the two registers. A Domino clock used to drive the Domino logic and a system clock used to drive the static CMOS logic ensures that correct test data is applied and read out from the hybrid circuit.

Abstract translation: 包括静态CMOS逻辑和Domino CMOS逻辑的混合CMOS电路配置包括围绕Domino逻辑的两个寄存器，以允许对该逻辑进行测试。 一个寄存器接收输入测试向量，如果寄存器输入不能直接访问，则直接通过一组主要输入或串行扫描链进行加载。 第二个寄存器锁存测试向量应用程序的结果。 如果在寄存器输出和主要电路输出之间没有静态CMOS逻辑，或者使用串行扫描链从第二个寄存器中扫描，寄存器内容可以直接通过一组主要输出读取。 Domino扫描触发器可以减少晶体管数量超过常规静态扫描触发器，可以在Domino逻辑中用作执行多种逻辑功能的顺序元件。 这些扫描触发器可以作为单独的扫描链的一部分串行连接，或者与电路中的寄存器和任何其他静态扫描触发器集成到单个扫描链中。 Domino扫描触发器允许所有标称逻辑与两个寄存器一起进行测试。 用于驱动Domino逻辑的Domino时钟和用于驱动静态CMOS逻辑的系统时钟可确保从混合电路应用和读出正确的测试数据。

公开(公告)号：US5670890A

公开(公告)日：1997-09-23

申请号：US533704

申请日：1995-09-26

Applicant: Michael Colwell ,  Rochit Rajsuman ,  Ray Abrishami ,  Zarir B. Sarkari

Inventor： Michael Colwell ,  Rochit Rajsuman ,  Ray Abrishami ,  Zarir B. Sarkari

IPC: G01R31/30 ,  G01R31/28

CPC classification number: G01R31/3004 ,  G01R31/3008

Abstract: An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

公开(公告)号：US5377148A

公开(公告)日：1994-12-27

申请号：US620359

申请日：1990-11-29

Applicant: Rochit Rajsuman

Inventor： Rochit Rajsuman

IPC: G11C29/10 ,  G11C29/28 ,  G11C29/44 ,  G11C7/00

CPC classification number: G11C29/44 ,  G11C29/10 ,  G11C29/28

Abstract: The present invention provides a test method of the complexity of 7n to test RAM devices, where n is the number of bits. This method tests all cell stuck-at-1/0 faults, state transition 1-to-0 and 0-to-1 faults, state coupling faults between two cells and data retention faults in random access memories. A standardized testable design memory (STD architecture) is presented which keeps the time required to test a RAM constant irrespective of the memory size. The design is shown through four examples to cover both bit and byte oriented memories. The memory address decoder is implemented in two or more levels. The decoder decoding the most significant addressed is modified by addition of an external control signal line. Memory of the RAM (memory cell array) is partitioned into blocks. The size of these blocks is defined by the last level (least significant address) of the memory address decoder. The design is highly structured and requires a very small amount of extra hardware. The architecture is not only applicable at chip level, but also at the board level. A slight modification allows fault diagnosis to be achieved in the STD architecture. This architecture also permits disconnection of faulty memory blocks and use the good part as 3/4 or 1/2 of the original capacity. Such reconfiguration in STD architecture can be done by specifying a fixed voltage (Gnd or Vdd) at the input of the most significant decoder. Such a reconfiguration does not require special hardware.

Abstract translation: 本发明提供了一种用于测试RAM设备的复杂度的测试方法，其中n是比特数。 这种方法测试所有单元卡在1/0故障，状态转换1到0和0到1故障，两个单元之间的状态耦合故障和随机存取存储器中的数据保留故障。 提供了标准化的可测试设计存储器（STD架构），其保持测试RAM常数所需的时间，而不管存储器大小如何。 该设计通过四个示例来显示，以覆盖位和字节的存储器。 存储器地址解码器以两个或更多个级别实现。 通过添加外部控制信号线来修改对最重要寻址的解码器解码。 RAM（存储单元阵列）的存储器被分割成块。 这些块的大小由存储器地址解码器的最后一级（最低有效地址）定义。 该设计结构高，需要非常少量的额外硬件。 架构不仅适用于芯片级，还适用于板级。 轻微修改允许在STD架构中实现故障诊断。 该架构还允许断开故障存储器块，并将良好部分用作原始容量的3/4或1/2。 STD架构中的这种重新配置可以通过在最重要的解码器的输入端指定固定电压（Gnd或Vdd）来完成。 这样的重新配置不需要特殊的硬件。

公开(公告)号：US07178115B2

公开(公告)日：2007-02-13

申请号：US10412143

申请日：2003-04-11

Applicant: Rochit Rajsuman ,  Hiroaki Yamoto

Inventor： Rochit Rajsuman ,  Hiroaki Yamoto

IPC: G06F17/50

CPC classification number: G01R31/318314 ,  G01R31/31704 ,  G01R31/31917 ,  G06F17/5022 ,  H01L27/118

Abstract: A manufacturing process for LSIs uses an event tester simulator and an event tester to avoid prototype hold. In the LSI manufacturing method an LSI is designed under an EDA (electronic design automation) environment to produce design data of a designed LSI, and logic simulation is performed on a device model of the LSI design in the EDA environment with use of a testbench and producing a test vector file of an event format as a result of the logic simulation. Then, simulation data files are verified with use of the design data and the testbench by operating an event tester simulator, and a prototype LSI is produced through a fabrication provider by using the design data. The prototype LSI is tested by an event tester by using the test vector file and the simulation data files and test results is feedbacked to the EDA environment or the fabrication provider.

Abstract translation: LSI的制造过程使用事件测试器模拟器和事件测试器来避免原型保持。 在LSI制造方法中，在EDA（电子设计自动化）环境下设计LSI以产生设计的LSI的设计数据，并且使用测试台在EDA环境中对LSI设计的设备模型进行逻辑模拟， 作为逻辑模拟的结果产生事件格式的测试向量文件。 然后，通过使用事件测试器模拟器，使用设计数据和测试平台验证仿真数据文件，并通过使用设计数据通过制造提供商生产原型LSI。 原型LSI由事件测试者通过​​使用测试矢量文件和仿真数据文件进行测试，测试结果反馈给EDA环境或制造商。

公开(公告)号：US06804620B1

公开(公告)日：2004-10-12

申请号：US10393876

申请日：2003-03-21

Applicant: Douglas Larson ,  Anthony Le ,  Carol Qiao Tong ,  Rochit Rajsuman

Inventor： Douglas Larson ,  Anthony Le ,  Carol Qiao Tong ,  Rochit Rajsuman

IPC: G06F900

CPC classification number: G01R31/3191 ,  G01R31/31922

Abstract: An ATE calibration method and system that does not require external test equipment to calibrate individual functional pins and provides balanced timing skews among the functional pins and pincards is disclosed. A functional pin in the test system is selected as a reference or “golden” pin and another is selected as a precision measurement unit (PMU). External test equipment and the reference PMU are used to measure the AC and DC characteristics of the reference pin, and any deviation represents a measurement error in the reference PMU. All functional pins in the test system can be measured against the reference pin using the reference PMU, taking into account the measurement error, without the need for external test equipment. To ensure that skews are balanced among all pins, the location of the reference pin is selected to be as close as possible to the midpoint of the functional pin range.

Abstract translation: 公开了一种不需要外部测试设备来校准各个功能引脚并在功能引脚和引脚卡之间提供平衡的时序偏移的ATE校准方法和系统。 选择测试系统中的功能引脚作为参考或“黄金”引脚，另一个选择为精密测量单元（PMU）。 外部测试设备和参考PMU用于测量参考引脚的交流和直流特性，任何偏差表示参考PMU中的测量误差。 测试系统中的所有功能引脚可以使用参考PMU测量参考引脚，同时考虑到测量误差，无需外部测试设备。 为了确保所有引脚之间的偏差平衡，参考引脚的位置选择为尽可能靠近功能引脚范围的中点。

公开(公告)号：US06747447B2

公开(公告)日：2004-06-08

申请号：US10254401

申请日：2002-09-25

Applicant: Niels Markert ,  Anthony Le ,  Robert Sauer ,  Rochit Rajsuman ,  Hiroki Yamoto

Inventor： Niels Markert ,  Anthony Le ,  Robert Sauer ,  Rochit Rajsuman ,  Hiroki Yamoto

IPC: G01R3102

CPC classification number: G01R31/2886

Abstract: The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved. Based on the profile of the cam slots, the loadboard assembly can be gradually lowered to achieve contact between the printed circuit board and the contact pins on the test head and to lock the interface board.

Abstract translation: 本发明涉及半导体测试装置装置的锁定装置和装载板组件。 装载板组件包括包含被测器件的印刷电路板和固定到印刷电路板底部的接口板。 接口板有两个成员之间有空格。 隔板连接构件以形成测试头上的接触针的孔。 装载板组件放置在安装在测试头的顶表面上的锁定装置的顶部上。 装载板在锁定装置上的布置根据延伸穿过接合板和装载板组件的印刷电路板中的两个孔的不同横截面的两个销进行。 当将装载板组件放置在锁定机构上时，安装在接口板上的辊被容纳在锁定装置的凸轮构件的凸轮槽中。 当凸轮构件移动时，这些滚轮跟随凸轮槽。 基于凸轮槽的轮廓，可以逐渐降低装载板组件以实现印刷电路板与测试头上的接触针之间的接触并锁定接口板。

公开(公告)号：US06651204B1

公开(公告)日：2003-11-18

申请号：US09585831

申请日：2000-06-01

Applicant: Rochit Rajsuman ,  Shigeru Sugamori ,  Hiroaki Yamoto

Inventor： Rochit Rajsuman ,  Shigeru Sugamori ,  Hiroaki Yamoto

IPC: G01R3128

CPC classification number: G01R31/31915

Abstract: An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.

Abstract translation: 基于事件的测试系统具有用于同时测试包括存储器和逻辑器件的多个半导体器件（DUT）的模块化架构。 测试系统检测DUT中的功能故障以及物理故障。 测试系统包括两个或多个测试器模块，每个测试模块具有多个引脚单元，用于容纳两个或更多个测试器模块的主框架，用于电连接测试器模块和DUT的测试夹具，用于控制整个操作的主计算机 的测试系统，以及用于存储用于产生用于测试存储器的存储器测试模式的算法测试模式和软件工具库的数据存储器。 存储器测试算法和有关要测试的存储器的设计和配置的信息在存储器测试之前被指定。

公开(公告)号：US06408412B1

公开(公告)日：2002-06-18

申请号：US09390064

申请日：1999-09-03

Applicant: Rochit Rajsuman

Inventor： Rochit Rajsuman

IPC: G06F1100

CPC classification number: G01R31/3167

Abstract: A method of testing an embedded analog core in an integrated circuit chip having a microprocessor core and a memory core. The method includes the steps of providing a test register in the integrated circuit chip between the microprocessor core and an analog core to be tested, testing the microprocessor core and the memory core, using an assembly language test program running on the microprocessor core to generate a test pattern by the microprocessor core, applying the test pattern to the analog core by the microprocessor core and evaluating the response of the analog core either by the microprocessor core or a test system provided outside of the integrated circuit chip.

Abstract translation: 一种在具有微处理器核心和存储器核心的集成电路芯片中测试嵌入式模拟核心的方法。 该方法包括以下步骤：使用在微处理器核心上运行的汇编语言测试程序，在微处理器核心和要测试的模拟核心之间的集成电路芯片中提供测试寄存器，测试微处理器核心和存储器核心，以产生 由微处理器核心的测试模式，通过微处理器核心将测试模式应用于模拟核心，并通过微处理器内核或集成电路芯片外提供的测试系统评估模拟核心的响应。