发明授权
US07190226B2 Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
有权
具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元
- 专利标题: Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
- 专利标题(中): 具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元
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申请号: US10928420申请日: 2004-08-27
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公开(公告)号: US07190226B2公开(公告)日: 2007-03-13
- 发明人: Debanjan Mukherjee , Jishnu Bhattacharjee
- 申请人: Debanjan Mukherjee , Jishnu Bhattacharjee
- 申请人地址: US CA San Jose
- 专利权人: Scintera Networks
- 当前专利权人: Scintera Networks
- 当前专利权人地址: US CA San Jose
- 代理机构: MacPherson Kwok Chen & Heid LLP
- 代理商 Gideon Gimlan
- 主分类号: H03F3/45
- IPC分类号: H03F3/45
摘要:
A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.
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