公开(公告)号：US08937993B2

公开(公告)日：2015-01-20

申请号：US13897119

申请日：2013-05-17

申请人： Scintera Networks LLC

发明人： Qian Yu ,  Yan Wang ,  Rajeev Krishnamoorthy

IPC分类号： H03H7/30 ,  H04B1/10 ,  H04B1/04

CPC分类号： H04L27/2624

摘要： A crest factor reduction (CFR) circuit reduces the peak-to-average (PAR) power of a digitally modulated signal in a complex baseband is achieved by post-processing the input signal, with negligible increase in out-of-band emissions. The CFR circuit takes advantage of a procedure that solves for an optimum CFR using a constraint-optimization approach. In one embodiment, the CFR circuit, which receives an input signal and provides an output signal, includes: (a) an error generation circuit that receives the input signal and provides an error signal representative of a measure of circuit-induced distortion and a delayed input signal, the delayed input signal being the input signal delayed by a predetermined value; (b) a linear-phase filter receiving the error signal to provide a correction signal; and (c) a summer that subtracts the correction from the delayed input signal to provide the output signal. This circuit can achieve near optimal CFR for arbitrary multi-carrier signals without incurring high computational complexity.

摘要翻译： 峰值因数降低（CFR）电路降低了复数基带中的数字调制信号的峰均比（PAR）功率，通过对输入信号进行后处理，带外发射的增加可以忽略不计。 CFR电路利用了使用约束优化方法解决最佳CFR的过程。 在一个实施例中，接收输入信号并提供输出信号的CFR电路包括：（a）误差产生电路，其接收输入信号并提供代表电路引起的失真的测量的误差信号和延迟的 输入信号，延迟输入信号是延迟预定值的输入信号; （b）接收误差信号以提供校正信号的线性相位滤波器; 和（c）从延迟的输入信号中减去校正以提供输出信号的加法器。 该电路可以实现任意多载波信号的接近最佳CFR，而不会导致高计算复杂度。

公开(公告)号：US08805304B2

公开(公告)日：2014-08-12

申请号：US13343631

申请日：2012-01-04

申请人： Qian Yu ,  Rajeev Krishnamoorthy ,  Olivier Charlon

发明人： Qian Yu ,  Rajeev Krishnamoorthy ,  Olivier Charlon

IPC分类号： H04B1/04

CPC分类号： H03F1/3258 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45376 ,  H03F3/45892 ,  H03F2200/336 ,  H03F2203/45394 ,  H03F2203/45562 ,  H03F2203/45614 ,  H03F2203/45616

摘要： An RF linearizer and an associated method are provided for linearizing a power amplifier. The RF linearizer may include: (a) a quadrature up-converter for up-converting a baseband input signal that is to be transmitted by the power amplifier; (b) an RF analog predistorter controlled by a set of coefficients for predistorting the up-converted input signal; (c) a down-converter for down-converting an output signal of the power amplifier; (d) an error monitor receiving the down-converted output signal and the input signal for providing an error signal; and (e) a signal analyzer receiving the error signal, the signal analyzer using an out-of-band power spectrum of the error signal to optimize the set of coefficients. The input signal may have an in-phase component and a quadrature component.

摘要翻译： 提供RF线性化器和相关联的方法用于线性化功率放大器。 RF线性化器可以包括：（a）用于上变频由功率放大器发送的基带输入信号的正交上变频器; （b）由一组系数控制的RF模拟预失真器，用于预失真上变频的输入信号; （c）用于对功率放大器的输出信号进行下变频的下变频器; （d）误差监视器，接收所述下变频输出信号和所述输入信号以提供误差信号; 以及（e）信号分析仪，其接收误差信号，所述信号分析仪使用所述误差信号的带外功率谱来优化所述系数集合。 输入信号可以具有同相分量和正交分量。

公开(公告)号：US08706062B1

公开(公告)日：2014-04-22

申请号：US12421324

申请日：2009-04-09

申请人： Qian Yu ,  Abhijit G Shanbhag ,  Yan Wang

发明人： Qian Yu ,  Abhijit G Shanbhag ,  Yan Wang

IPC分类号： H01Q11/12

CPC分类号： H03F3/245 ,  H03F1/3223 ,  H03F1/3247 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/336 ,  H03F2201/3209 ,  H03F2201/3224 ,  H03F2203/21106 ,  H03F2203/21142

摘要： In one embodiment a mixed-signal adaptive integrated circuit is comprised of a pre-distortion circuit operable to receive an RF input signal and to add a pre-distortion signal to the RF input signal to thereby provide a pre-distorted RF input signal, and a power amplifier coupled to the pre-distortion circuit and operable to receive the pre-distorted RF input signal and to provide an amplified RF output signal. The circuit further comprises a compensation module operable to receive the RF input signal and to provide a compensation signal, an auxiliary amplifier coupled to the compensation module and operable to selectively add the compensation signal to the amplified RF output signal, and a signal analyzer operable to receive and process the RF input signal and an RF output feedback signal to generate a first digital control signal for the pre-distortion circuit and a second digital control signal for the compensation module. A method for adaptive control of such a mixed-signal integrated circuit is also provided.

摘要翻译： 在一个实施例中，混合信号自适应集成电路包括预失真电路，其可操作以接收RF输入信号并将预失真信号添加到RF输入信号，从而提供预失真的RF输入信号，以及 功率放大器，其耦合到所述预失真电路并且可操作以接收所述预失真的RF输入信号并提供放大的RF输出信号。 该电路还包括可操作以接收RF输入信号并提供补偿信号的补偿模块，耦合到补偿模块的辅助放大器，其可操作以选择性地将补偿信号添加到放大的RF输出信号，以及信号分析器，其可操作以 接收和处理RF输入信号和RF输出反馈信号以产生用于预失真电路的第一数字控制信号和用于补偿模块的第二数字控制信号。 还提供了一种用于这种混合信号集成电路的自适应控制的方法。

公开(公告)号：US20140009228A1

公开(公告)日：2014-01-09

申请号：US13954497

申请日：2013-07-30

申请人： Scintera Networks, Inc.

发明人： Kelly Davidson HAWKES

IPC分类号： H03F1/32

CPC分类号： H03F1/3247 ,  H03F1/3294 ,  H03F2200/192 ,  H03F2200/195 ,  H03F2200/204 ,  H03F2200/207 ,  H03F2200/228

摘要： An apparatus and a method select and use parameter values for an RF power amplifier linearizer to pre-distort the input signals of a power amplifier, so as to achieve a linear output response in the power amplifier. The apparatus and the method select from a number of sets of parameter values, each set of parameter values corresponding to a different output power range of the power amplifier. The set of parameters include a coefficient vector tailored for the particular output power range for that set. The power amplifier input power is repeatedly measured and filtered at various time intervals. The input power measurements may be filtered by a fast attack/slow decay filter, which follows the peaks of the measurements under operation of the fast attack portion of the filter and provides a low variance during operation of the slow decay portion of the filter.

摘要翻译： 一种装置和方法选择并使用RF功率放大器线性化器的参数值来预失真功率放大器的输入信号，从而在功率放大器中实现线性输出响应。 该装置和方法从多个参数值集合中选择每一组对应于功率放大器的不同输出功率范围的参数值。 该组参数包括针对该组的特定输出功率范围量身定制的系数向量。 功率放大器输入功率以不同的时间间隔重复测量和滤波。 输入功率测量可以通过快速攻击/慢衰减滤波器来滤波，该滤波器跟随滤波器的快速攻击部分操作的测量的峰值，并且在滤波器的缓慢衰减部分的操作期间提供低的方差。

公开(公告)号：US08519789B2

公开(公告)日：2013-08-27

申请号：US13197691

申请日：2011-08-03

申请人： Kelly Davidson Hawkes

发明人： Kelly Davidson Hawkes

IPC分类号： H03F1/26

CPC分类号： H03F1/3247 ,  H03F1/3294 ,  H03F2200/192 ,  H03F2200/195 ,  H03F2200/204 ,  H03F2200/207 ,  H03F2200/228

摘要： An apparatus and a method select and use parameter values for an RF power amplifier linearizer to pre-distort the input signals of a power amplifier, so as to achieve a linear output response in the power amplifier. The apparatus and the method select from a number sets of parameter values, each set of parameter values corresponding to a different output power range of the power amplifier. The set of parameters include a coefficient vector tailored for the particular output power range for that set. The power amplifier input power is repeatedly measured and filtered at various time intervals. The input power measurements may be filtered by a fast attack/slow decay filter, which follows the peaks of the measurements under operation of the fast attack portion of the filter and provides a low variance during operation of the slow decay portion of the filter. The coefficient values for the predistortion linearization of the power amplifier is adapted dynamically, in response to changes in the input power level of the power amplifier. In one embodiment, hysteresis is used to reduce the rate at which the predistortion linearizer hops between two sets of the parameter values. Using the apparatus and the method, good ACLR across a wide range of power amplifier output power is achieved. Such characteristics are particularly advantageous in a system in which waveforms having fast power transients are present.

摘要翻译： 一种装置和方法选择并使用RF功率放大器线性化器的参数值来预失真功率放大器的输入信号，从而在功率放大器中实现线性输出响应。 该装置和方法从多组参数值中选择每组与功率放大器的不同输出功率范围对应的参数值。 该组参数包括针对该组的特定输出功率范围量身定制的系数向量。 功率放大器输入功率以不同的时间间隔重复测量和滤波。 输入功率测量可以通过快速攻击/慢衰减滤波器来滤波，该滤波器跟随滤波器的快速攻击部分操作的测量的峰值，并且在滤波器的缓慢衰减部分的操作期间提供低的方差。 响应于功率放大器的输入功率电平的变化，功率放大器的预失真线性化的系数值被动态地适配。 在一个实施例中，使用滞后来降低预失真线性化器在两组参数值之间跳跃的速率。 使用该装置和方法，实现了广泛的功率放大器输出功率的良好的ACLR。 在存在具有快速功率瞬变的波形的系统中，这种特性是特别有利的。

公开(公告)号：US08331487B2

公开(公告)日：2012-12-11

申请号：US12939067

申请日：2010-11-03

申请人： Qian Yu ,  Frédéric Roger ,  Adric Q. Broadwell ,  Olivier Charlon

发明人： Qian Yu ,  Frédéric Roger ,  Adric Q. Broadwell ,  Olivier Charlon

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC分类号： H03F1/3241 ,  H03F3/19 ,  H03F2201/3224 ,  H04B2001/0425

摘要： RF predistortion apparatus for making linear the output signal of non-linear components such as RF power amplifiers. The apparatus comprises an RF input line for carrying an RF signal connected to an envelope detector for finding the envelope of the RF signal, a power detector for finding the power of the RF signal and a quadrature modulator. The apparatus also comprises a coefficient vector input line for carrying an input signal that carries one or more coefficients to a digitally controlled analog subsystem (DCAS). The DCAS having circuitry for processing both the output of the envelope detector and the output of the power detector by selecting one or more coefficients from the coefficient vector input line for generating a weighted summation of the power of the RF signal and a weighted summation of the envelope voltage of the RF signal that are output to the quadrature modulator. The quadrature modulator has circuitry for mixing the RF input signal with the output of the DCAS to generate a signal for predistorting the RF input signal feeding the power amplifier.

摘要翻译： 射频预失真装置，用于对诸如RF功率放大器之类的非线性分量的输出信号进行线性化。 该装置包括用于携带连接到包络检测器的RF信号的RF输入线，用于找到RF信号的包络，用于找到RF信号的功率的功率检测器和正交调制器。 该装置还包括一个用于承载一个或多个系数到数字控制的模拟子系统（DCAS）的输入信号的系数向量输入线。 DCAS具有用于通过从系数向量输入线中选择一个或多个系数来处理包络检测器的输出和功率检测器的输出的电路，用于产生RF信号的功率的加权求和和 输出到正交调制器的RF信号的包络电压。 正交调制器具有用于将RF输入信号与DCAS的输出混合以产生用于预失真馈送功率放大器的RF输入信号的信号的电路。

公开(公告)号：US08295394B1

公开(公告)日：2012-10-23

申请号：US12257292

申请日：2008-10-23

申请人： Adric Q. Broadwell ,  Armando C. Cova ,  Frederic Roger ,  Qian Yu

发明人： Adric Q. Broadwell ,  Armando C. Cova ,  Frederic Roger ,  Qian Yu

IPC分类号： H04K1/02

CPC分类号： H03F1/3247 ,  H03F2201/3224

摘要： A performance monitor for generating a digital error signal based upon an RF input signal and an amplified RF output signal is provided. The monitor includes: a first analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase (Q) version of the RF input signal responsive to a first clock signal to provide a first digital I signal and a first digital Q signal; a second analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase version of the amplified RF output signal responsive to a second clock signal to provide a second digital I signal and a second digital Q signal; a first adaptive delay filter to delay the first digital I signal and the first digital Q signal to provide a first delayed complex signal according to a first delay; a second adaptive filter to delay the second digital I signal and the second digital Q signals to provide a second delayed complex signal according to a second delay; a complex gain matching adder operable to add a complex gain matching factor to a selected one of the delayed complex signals to provide a gain matched complex signal; and an adder to add the gain matched complex signal to a remaining one of the first and second delayed complex signals to provide the digital error signal.

摘要翻译： 提供了一种用于基于RF输入信号和放大的RF输出信号产生数字误差信号的性能监视器。 监视器包括：第一模数转换器，用于响应于第一时钟信号数字化RF输入信号的同相（I）和正交相位（Q）版本，以提供第一数字I信号和 第一数字Q信号; 第二模数转换器，用于响应于第二时钟信号数字化放大的RF输出信号的同相（I）和正交相位版本，以提供第二数字I信号和第二数字Q信号; 第一自适应延迟滤波器，用于延迟第一数字I信号和第一数字Q信号，以根据第一延迟提供第一延迟复信号; 第二自适应滤波器，用于延迟所述第二数字I信号和所述第二数字Q信号，以根据第二延迟提供第二延迟复信号; 复增益匹配加法器，用于将复增益匹配因子添加到所选延迟复信号中的一个以提供增益匹配复信号; 以及加法器，用于将增益匹配复信号与第一和第二延迟复数信号中的剩余的一个相加，以提供数字误差信号。

公开(公告)号：US08229027B2

公开(公告)日：2012-07-24

申请号：US12909649

申请日：2010-10-21

申请人： Arvind Keerthi ,  Madabusi Govindarajan ,  P. Vijay Kumar ,  John Choma ,  Abhijit Shanbhag

发明人： Arvind Keerthi ,  Madabusi Govindarajan ,  P. Vijay Kumar ,  John Choma ,  Abhijit Shanbhag

IPC分类号： H04K1/02 ,  H04L25/03 ,  H04L25/49

CPC分类号： H04L27/368 ,  H03F1/0222 ,  H03F1/0266 ,  H03F1/3211 ,  H03F1/3247 ,  H03F1/3258 ,  H03F3/45183 ,  H03F2200/102 ,  H03F2200/369 ,  H03F2200/451 ,  H03F2203/45352

摘要： Pre-distortion and memory compensation apparatuses and methods for a non-linear component are provided. The apparatus comprises an adaptive block for generating a plurality of correlation coefficients, which are used to weight a plurality of synthesis work functions to pre-distort a given signal. The adaptive block can be driven by an error signal generated from a feedback signal from the non-linear component output signal and a delayed version of the input signal. The apparatus is capable of being operated directly at radio frequency. Also provided are apparatuses and methods for generation of quadrature signals, transconductance amplification employing negative resistance, variable-gain amplification, and envelope detection.

摘要翻译： 提供了用于非线性分量的预失真和存储器补偿装置和方法。 该装置包括用于产生多个相关系数的自适应块，其用于加权多个合成工作函数以对给定信号进行预失真。 自适应块可以由从非线性分量输出信号的反馈信号和输入信号的延迟版本产生的误差信号驱动。 该装置能够以射频直接操作。 还提供了用于产生正交信号，采用负电阻的跨导放大，可变增益放大和包络检测的装置和方法。

公开(公告)号：US08145150B1

公开(公告)日：2012-03-27

申请号：US12340032

申请日：2008-12-19

申请人： Qian Yu ,  Abhijit G. Shanbhag ,  Yan Wang

发明人： Qian Yu ,  Abhijit G. Shanbhag ,  Yan Wang

IPC分类号： H04B1/04

CPC分类号： H03F1/3241 ,  H03F1/3247 ,  H04B17/13

摘要： A mixed-signal adaptive integrated circuit may comprise a primary function circuit, a digitally controlled analog sub-system cooperatively connected with the primary function circuit, and an on-chip signal analyzer. The on-chip signal analyzer may be arranged to analyze RF signals. The signal analyzer may comprise at least one multiplexor for selecting selected RF signals for comparison and analysis, and may comprise a digital signal processor (DSP) for analyzing the selected RF signals and adjusting at least one operational parameter of the digitally controlled analog sub-system responsive to the analysis.

摘要翻译： 混合信号自适应集成电路可以包括与主要功能电路协作连接的主要功能电路，数字控制的模拟子系统和片上信号分析器。 片上信号分析器可以被布置成分析RF信号。 信号分析器可以包括用于选择用于比较和分析的所选RF信号的至少一个多路复用器，并且可以包括用于分析所选择的RF信号并调整数字控制的模拟子系统的至少一个操作参数的数字信号处理器（DSP） 响应分析。

公开(公告)号：US07627031B2

公开(公告)日：2009-12-01

申请号：US11186241

申请日：2005-07-21

申请人： Qian Yu ,  Venugopal Balasubramonian ,  Jishnu Bhattacharjee ,  Debanjan Mukherjee ,  Abhijit Phanse ,  Abhijit G. Shanbhag ,  Edem Ibragimov ,  Fabian Giroud

发明人： Qian Yu ,  Venugopal Balasubramonian ,  Jishnu Bhattacharjee ,  Debanjan Mukherjee ,  Abhijit Phanse ,  Abhijit G. Shanbhag ,  Edem Ibragimov ,  Fabian Giroud

IPC分类号： H03H7/30

CPC分类号： H04L7/0062 ,  H04L7/0029 ,  H04L25/03057 ,  H04L2025/03503

摘要： An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

摘要翻译： 一种用于自适应地引入与数据符号判定电路的信号等待时间相关的补偿信号延迟的装置和方法。 自适应定时控制电路，包括实现为具有相关抽头系数的抽头延迟线的内插混频器，自适应地和基本上匹配数据判决电路的等待时间以在自适应均衡器内使用，从而最小化这样的均方误差 决策电路。 该自适应等待时间用于产生反馈误差信号，反馈误差信号又可由前馈均衡器用于动态调整其自适应滤波器抽头系数。