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    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
    2.
    发明授权
    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权
    具有更均匀分布的容性负载的模拟延迟链和用于链中的模拟延迟单元

    公开(公告)号：US07190226B2

    公开(公告)日：2007-03-13

    申请号：US10928420

    申请日：2004-08-27

    申请人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    发明人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45183 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45652 ,  H03F2203/45688 ,  H03F2203/45712

    摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.

    摘要翻译： 抽头延迟链包括多个延迟单元，其中每个单元具有至少两个输出抽头：用于将延迟的信号馈送到链中的下一个单元的初级延迟单元，以及用于馈送稍微不同的延迟信号的次级输出抽头 到乘法器单元，使得略微不同的延迟信号可以乘以加权系数。 每个延迟单元中的输出抽头分开允许相应的负载电容分流。 延迟单元的每个输出抽头加载的电容小于如果分裂抽头被集中在一起作为公共节点而不得不以其他方式驱动的电容。 每个分接抽头的减小的负载电容允许更宽的频率响应范围。 抽头延迟链可用于形成前馈均衡器（FFE），该前馈均衡器还包括加法器和多个乘法器，每个乘法器分别接收延迟的输入信号（（延迟）） 链中相应的延迟单元的辅助输出抽头，并且每个输出相应的延迟加权乘积信号（Pi）给加法器。

    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain
    4.
    发明申请
    Analog delay chain having more uniformly distributed capacitive loads and analog delay cell for use in chain 有权

    公开(公告)号：US20070115074A1

    公开(公告)日：2007-05-24

    申请号：US11640079

    申请日：2006-12-15

    申请人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    发明人： Debanjan Mukherjee ,  Jishnu Bhattacharjee

    IPC分类号： H04B3/14

    CPC分类号： H03F3/45183 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45652 ,  H03F2203/45688 ,  H03F2203/45712

    摘要： A tapped delay chain comprises a plurality of delay cells where each cell has at least two output taps: a primary one for feeding forward a delayed signal to a next cell in the chain, and a secondary output tap for feeding a slightly-differently delayed signal to a multiplier unit so that the slightly-differently delayed signal can be multiplied by a weighting coefficient. The split of output taps in each delay cell allows for a corresponding split of loading capacitance. Each output tap of the delay cell is loaded by a smaller capacitance than it would have had to otherwise drive had the split taps been instead lumped together as a common node. The reduced loading capacitance at each of the split taps allows for a wider frequency response range. The tapped delay chain may be used to form a feed-forward equalizer (FFE) which further comprises an adder, and a plurality of multipliers each respectively receiving a delayed input signal (Sin(delayed)) from a secondary output tap of a respective delay cell in the chain and each outputting a correspondingly delayed and weighted, product signal (Pi) to the adder.

    Low voltage broadband gain cell
    5.
    发明申请
    Low voltage broadband gain cell 有权
    低电压宽带增益电池

    公开(公告)号：US20060061415A1

    公开(公告)日：2006-03-23

    申请号：US10946738

    申请日：2004-09-21

    申请人： Jishnu Bhattacharjee ,  Debanjan Mukherjee

    发明人： Jishnu Bhattacharjee ,  Debanjan Mukherjee

    IPC分类号： G06G7/12

    CPC分类号： H03F1/42 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2200/39 ,  H03F2203/45361 ,  H03F2203/45638 ,  H03F2203/45641 ,  H03F2203/45652 ,  H03F2203/45686 ,  H03F2203/45702 ,  H03F2203/45704 ,  H03F2203/45706 ,  H03F2203/45731

    摘要： T-coil structures are used in one embodiment to inject programmably-variable amounts of transistor biasing currents into the respective drains of current sinking transistor means of a broadband differential amplifier such that, when the differential amplifier is in common mode, total transistor drain current will exceed total voltage-dropping current passing through corresponding voltage-dropping resistances of the amplifier's transistor means. The T-coil structures keep the parasitic capacitances of the programmable current sources that provide the bias currents de-lumped from capacitances of the amplifier's output nodes and/or capacitances of the amplifier's voltage-dropping resistances (variable resistances) to thereby maintain a wide bandwidth.

    摘要翻译： 在一个实施例中使用T形线圈结构，以将可编程可变量的晶体管偏置电流注入到宽带差分放大器的电流吸收晶体管装置的相应漏极中，使得当差分放大器处于共模时，总晶体管漏极电流将 超过通过放大器晶体管装置的相应降压电阻的总压降电流。 T线圈结构保持可编程电流源的寄生电容，其提供从放大器的输出节点的电容和/或放大器的降压电阻（可变电阻）的电容中解除的偏置电流，从而保持宽带宽 。

    Reference generator
    6.
    发明授权
    Reference generator 有权
    参考发生器

    公开(公告)号：US06965337B1

    公开(公告)日：2005-11-15

    申请号：US10899498

    申请日：2004-07-26

    申请人： Jishnu Bhattacharjee ,  Debanjan Mukherjee ,  Fabian Giroud

    发明人： Jishnu Bhattacharjee ,  Debanjan Mukherjee ,  Fabian Giroud

    IPC分类号： H03K5/24 ,  H03M1/12

    CPC分类号： H03K5/2481

    摘要： Systems and methods are disclosed herein to provide reference generators. For example, in accordance with an embodiment of the present invention, a reference generator is provided for an electrical device, such as for example for an analog-to-digital converter. The reference generator may provide one or more reference signals having a common mode voltage that can track or be varied based on a common mode voltage of an input signal. Alternatively or in addition, the reference generator may provide reference signals for single-ended applications.

    摘要翻译： 本文公开了系统和方法以提供参考发生器。 例如，根据本发明的实施例，为电气设备提供参考发生器，例如用于模数转换器。 参考发生器可以提供具有可以基于输入信号的共模电压跟踪或变化的共模电压的一个或多个参考信号。 或者或另外，参考发生器可为单端应用提供参考信号。

    Equalizer systems and methods utilizing analog delay elements
    9.
    发明授权
    Equalizer systems and methods utilizing analog delay elements 有权
    使用模拟延迟元件的均衡器系统和方法

    公开(公告)号：US08117249B1

    公开(公告)日：2012-02-14

    申请号：US11926869

    申请日：2007-10-29

    申请人： Debanjan Mukherjee ,  Jishnu Bhattacharjee ,  Qian Yu ,  Abhijit Phanse

    发明人： Debanjan Mukherjee ,  Jishnu Bhattacharjee ,  Qian Yu ,  Abhijit Phanse

    IPC分类号： G06F17/10

    CPC分类号： H03F3/45183 ,  H03F2203/45634 ,  H03F2203/45638 ,  H03H11/265 ,  H03H15/02 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： Systems and methods provide analog delay elements, which may be utilized in isolation or in a cascade, such as for use within equalizers or other types of applications. For example, a delay element may include a broadband amplifier and a passive, programmable filter, which may provide a desired magnitude and group delay response over a wide frequency range while being tolerant of process variations. An equalizer, for example, may include the delay element within its feed forward filter and/or within its other circuits, such as within its adaptive coefficient generator or slicer input time-align circuit.

    摘要翻译： 系统和方法提供模拟延迟元件，其可以在隔离或级联中使用，例如用于均衡器或其他类型的应用中。 例如，延迟元件可以包括宽带放大器和无源可编程滤波器，其可以在宽的频率范围内提供期望的幅度和组延迟响应，同时容忍工艺变化。 例如，均衡器可以包括其前馈滤波器内和/或其其它电路内的延迟元件，例如在其自适应系数发生器或限幅器输入时间对准电路内。