发明授权
- 专利标题: Single-stage and multi-stage low power interconnect architectures
- 专利标题(中): 单级和多级低功率互连架构
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申请号: US11314236申请日: 2005-12-22
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公开(公告)号: US07190286B2公开(公告)日: 2007-03-13
- 发明人: Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I. Ismail
- 申请人: Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I. Ismail
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Fleshner & Kim, LLP
- 主分类号: H03M7/46
- IPC分类号: H03M7/46 ; H03M7/00
摘要:
An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
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