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公开(公告)号：US09484917B2
公开(公告)日：2016-11-01
申请号：US13718372
申请日：2012-12-18
CPC分类号： H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
摘要： Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.
摘要翻译： 描述了一种装置，其包括：耦合在第一电源和第二电源之间的夹具; 以及用于与第二电源操作的电路，其中当所述设备进入低功率模式时，所述钳位器可操作以调节所述第二电源。
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2.发明授权Performing variation-aware profiling and dynamic core allocation for a many-core processor 有权为多核处理器执行变化感知分析和动态核心分配公开(公告)号：US09063730B2
公开(公告)日：2015-06-23
申请号：US12972985
申请日：2010-12-20
申请人： Saurabh Dighe , Sriram R. Vangal , Nitin Y. Borkar , Vivek K. De
发明人： Saurabh Dighe , Sriram R. Vangal , Nitin Y. Borkar , Vivek K. De
CPC分类号： G06F1/3206 , G06F1/329 , G06F9/4893 , Y02D10/24
摘要： In one embodiment, the present invention includes a processor with multiple cores each having a self-test circuit to determine a frequency profile and a leakage power profile of the corresponding core. In turn, a scheduler is coupled to receive the frequency profiles and the leakage power profiles and to schedule an application on at least some of the cores based on the frequency profiles and the leakage power profiles. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个核心的处理器，每个核心具有自检电路，以确定相应核心的频率分布和泄漏功率分布。 反过来，调度器被耦合以接收频率分布和泄漏功率分布，并且基于频率分布和泄漏功率分布来在至少一些核上调度应用。 描述和要求保护其他实施例。
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3.发明授权Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode 有权用于指定和保存寄存器子集的单个指令，指定在唤醒后执行的工作监视功能的指针，以及进入低功耗模式公开(公告)号：US08762692B2
公开(公告)日：2014-06-24
申请号：US11904395
申请日：2007-09-27
申请人： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M Kuttanna , Asit Mallick , Vivek K De , Per Hammarlund
发明人： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M Kuttanna , Asit Mallick , Vivek K De , Per Hammarlund
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
摘要翻译： 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。
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公开(公告)号：US20100219516A1
公开(公告)日：2010-09-02
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译： 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。
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公开(公告)号：US20100145895A1
公开(公告)日：2010-06-10
申请号：US12704789
申请日：2010-02-12
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译： 系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及 温度信息。 一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。
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6.发明申请公开(公告)号：US20090089562A1
公开(公告)日：2009-04-02
申请号：US11904395
申请日：2007-09-27
申请人： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
发明人： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
IPC分类号： G06F9/312
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
摘要： Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
摘要翻译： 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。
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公开(公告)号：US20090003108A1
公开(公告)日：2009-01-01
申请号：US11772151
申请日：2007-06-30
申请人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Nam Sung Kim , Vivek K. De
发明人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Nam Sung Kim , Vivek K. De
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/08 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/005
摘要： In one embodiment, a memory system having a selectable configuration for sense amplifiers is disclosed. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.
摘要翻译： 在一个实施例中，公开了一种具有用于读出放大器的可选配置的存储器系统。 存储器系统可以包括位单元和耦合到位单元和读出放大器的第一部分的开关模块。 开关模块可以基于对读出放大器的第一部分的输入偏移电压的测试来连接，断开或将该位单元交叉耦合到读出放大器。 类似的配置可以由读出放大器的第二部分来实现。 该系统还可以包括用于配置开关模块的设置的编程器模块，并且可以包括列选择模块，以便基于要读取的位单元的列来将位单元耦合到读出放大器。 还公开了其他实施例。
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公开(公告)号：US07391640B2
公开(公告)日：2008-06-24
申请号：US11008666
申请日：2004-12-10
申请人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
发明人： Stephen H. Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad M. Khellah , Yibin Ye , Shih-Lien L. Lu , Vivek K. De
CPC分类号： G11C11/405 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
摘要翻译： 动态随机存取存储器包括具有浮体晶体管和位线之间的电路的单元。 控制电路的激活以在写入操作期间和在单元未被选择的时间期间在浮体和位线电压之间提供隔离。 增加的隔离可以提高性能，例如，通过减少门到体耦合的需要和位线之间的电压摆幅的大小。
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9.发明授权Method, apparatus and system of adjusting one or more performance-related parameters of a processor 有权调整处理器的一个或多个性能相关参数的方法，装置和系统公开(公告)号：US07376849B2
公开(公告)日：2008-05-20
申请号：US10879486
申请日：2004-06-30
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要翻译： 本发明的实施例提供了一种用于基于与处理器核心的操作条件相关的至少一个操作参数来动态地调整处理器核心的一个或多个与性能有关的参数的方法，装置和系统。
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公开(公告)号：US07315463B2
公开(公告)日：2008-01-01
申请号：US10956192
申请日：2004-09-30
申请人： Gerhard Schrom , Peter Hazucha , Donald S. Gardner , Vivek K. De , Tanay Karnik
发明人： Gerhard Schrom , Peter Hazucha , Donald S. Gardner , Vivek K. De , Tanay Karnik
IPC分类号： H02M5/00
CPC分类号： H02M3/1584 , H01F27/38 , H01F27/42 , H01F37/00 , H01F2038/026
摘要： A method and apparatus for multi-phase transformers are described. In one embodiment, a coupled inductor topology for the multi-phase transformers comprising N primary inductors. In one embodiment, each primary inductor is coupled to one of N input nodes and a common output node. The transformer further includes N−1 secondary inductors coupled in series between one input node and the common output node. In one embodiment, the N−1 secondary inductors are arranged to couple energy from N−1 of the primary inductors to provide a common node voltage as an average of N input node voltages, wherein N is an integer greater than two. Other embodiments are described and claimed.
摘要翻译： 描述了用于多相变压器的方法和装置。 在一个实施例中，用于包括N个初级电感器的多相变压器的耦合电感器拓扑。 在一个实施例中，每个主电感器耦合到N个输入节点和公共输出节点之一。 变压器还包括串联耦合在一个输入节点和公共输出节点之间的N-1个次级电感器。 在一个实施例中，N-1次级电感器被布置成耦合来自初级电感器的N-1的能量，以提供公共节点电压作为N个输入节点电压的平均值，其中N是大于2的整数。 描述和要求保护其他实施例。
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