Invention Grant
- Patent Title: Single-stage and multi-stage low power interconnect architectures
- Patent Title (中): 单级和多级低功率互连架构
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Application No.: US11314236Application Date: 2005-12-22
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Publication No.: US07190286B2Publication Date: 2007-03-13
- Inventor: Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I. Ismail
- Applicant: Maged M. Ghoneima , Peter Caputa , Muhammad M. Khellah , Ram Krishnamurthy , James W. Tschanz , Yiben Ye , Vivek K. De , Yehea I. Ismail
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Fleshner & Kim, LLP
- Main IPC: H03M7/46
- IPC: H03M7/46 ; H03M7/00
Abstract:
An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.
Public/Granted literature
- US20060109028A1 Single-stage and multi-stage low power interconnect architectures Public/Granted day:2006-05-25
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