发明授权
US07195976B2 Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
有权
非易失性半导体存储器及其制造方法,以及半导体器件及其制造方法
- 专利标题: Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
- 专利标题(中): 非易失性半导体存储器及其制造方法,以及半导体器件及其制造方法
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申请号: US10851350申请日: 2004-05-24
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公开(公告)号: US07195976B2公开(公告)日: 2007-03-27
- 发明人: Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
- 申请人: Tetsuo Adachi , Masataka Kato , Toshiakl Nishimoto , Nozomu Matsuzaki , Takashi Kobayashi , Yoshimi Sudou , Toshiyuki Mine
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Antonelli, Terry, Stout and Kraus, LLP
- 优先权: JP9-77175 19970328; JP9-182102 19970708
- 主分类号: H01L21/8247
- IPC分类号: H01L21/8247
摘要:
A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.