公开(公告)号：US06461916B1

公开(公告)日：2002-10-08

申请号：US09402078

申请日：2000-02-07

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07195976B2

公开(公告)日：2007-03-27

申请号：US10851350

申请日：2004-05-24

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US06444554B1

公开(公告)日：2002-09-03

申请号：US10011731

申请日：2001-12-11

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21283

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07692234B2

公开(公告)日：2010-04-06

申请号：US11862928

申请日：2007-09-27

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07528036B2

公开(公告)日：2009-05-05

申请号：US11107826

申请日：2005-04-18

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US20090230453A1

公开(公告)日：2009-09-17

申请号：US11862928

申请日：2007-09-27

申请人： Tetsuo ADACHI ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo ADACHI ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US20060051977A1

公开(公告)日：2006-03-09

申请号：US11266430

申请日：2005-11-04

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/31

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US20050189579A1

公开(公告)日：2005-09-01

申请号：US11107826

申请日：2005-04-18

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01M10/0525 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/283 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/76 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01M2/16

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US07304345B2

公开(公告)日：2007-12-04

申请号：US11266430

申请日：2005-11-04

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07141475B2

公开(公告)日：2006-11-28

申请号：US10954102

申请日：2004-09-30

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.