Invention Grant
US07196392B2 Semiconductor structure for isolating integrated circuits of various operation voltages
有权
用于隔离各种工作电压的集成电路的半导体结构
- Patent Title: Semiconductor structure for isolating integrated circuits of various operation voltages
- Patent Title (中): 用于隔离各种工作电压的集成电路的半导体结构
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Application No.: US11136810Application Date: 2005-05-24
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Publication No.: US07196392B2Publication Date: 2007-03-27
- Inventor: Jun-Xiu Liu , Chi-Hsuen Chang , Tzu-Chiang Sung , Chung-I Chen , Chih Po Huang
- Applicant: Jun-Xiu Liu , Chi-Hsuen Chang , Tzu-Chiang Sung , Chung-I Chen , Chih Po Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Kirkpatrick & Lockhart Preston Gates Ellis LLP
- Main IPC: H01L29/00
- IPC: H01L29/00

Abstract:
A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.
Public/Granted literature
- US20060113571A1 Semiconductor structure for isolating integrated circuits of various operation voltages Public/Granted day:2006-06-01
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