Invention Grant
- Patent Title: Semiconductor memory and method for operating the same
- Patent Title (中): 半导体存储器及其操作方法
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Application No.: US11265229Application Date: 2005-11-03
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Publication No.: US07203115B2Publication Date: 2007-04-10
- Inventor: Satoshi Eto
- Applicant: Satoshi Eto
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Arent Fox, PLLC.
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A data additional circuit adds plural types of expectation data to be read from a refresh block to data read from other blocks, respectively, to generate plural read data strings. An error correction circuit detects errors for each read data string, and sets the most reliable result of the error detection results to be true. The error correction circuit decodes data to be read from the refresh block based on a true error detection result. Moreover, the error correction circuit corrects the error of the read data string corresponding to the true error detection result. Consequently, without extending the read cycle time, a refresh operation can be hid, and errors can be corrected simultaneously. By correcting a data error read from a bad memory cell of data retention characteristics, a refresh request interval can be extended, and power consumption during a standby period can be reduced.
Public/Granted literature
- US20060056258A1 Semiconductor memory and method for operating the same Public/Granted day:2006-03-16
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