公开(公告)号：US07818516B2

公开(公告)日：2010-10-19

申请号：US11442576

申请日：2006-05-30

Applicant: Kuninori Kawabata ,  Satoshi Eto ,  Toshiya Miyo

Inventor： Kuninori Kawabata ,  Satoshi Eto ,  Toshiya Miyo

IPC: G06F13/00

CPC classification number: G06F13/1694 ,  G06F12/02

Abstract: A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.

Abstract translation: 连接到存储器的存储器控​​制器包括：地址接收单元，用于接收与命令一起外部输入的地址码; 以及命令转换单元，用于当与第一命令一起输入的地址代码指定未实现存储器的地址空间时，向存储器输出用于基于地址代码改变存储器的内部设置的MRS命令。

公开(公告)号：US07599244B2

公开(公告)日：2009-10-06

申请号：US11437719

申请日：2006-05-22

Applicant: Satoshi Eto ,  Kuninori Kawabata ,  Toshiya Miyo ,  Yuji Serizawa

Inventor： Satoshi Eto ,  Kuninori Kawabata ,  Toshiya Miyo ,  Yuji Serizawa

IPC: G11C8/00

CPC classification number: G11C7/20 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/225

Abstract: A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.

Abstract translation: 用于与时钟同步地输入和输出数据的半导体存储器包括用于接收时钟的时钟接收单元和用于在低功率待机之后最初接收与开启电源之后的时钟同步的第一特定命令的命令接收单元 或者在初始化之后，接着开始命令接收。

公开(公告)号：US20080298159A1

公开(公告)日：2008-12-04

申请号：US12129433

申请日：2008-05-29

Applicant: Kuninori Kawabata ,  Yoshiyuki Ishida ,  Satoshi Eto

Inventor： Kuninori Kawabata ,  Yoshiyuki Ishida ,  Satoshi Eto

IPC: G11C8/18

CPC classification number: G11C7/10

Abstract: An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced.

Abstract translation: 接口转换宏将符合从控制器输出的系统接口规范的信号转换为符合存储器接口规范的信号，并将其输出到存储器接口部分，并且还将从存储器宏输出的信号转换为 信号符合系统接口规范，并将其输出到控制器。 通过接口转换宏将系统接口规范和存储器接口规范相互转换，即使系统接口规范不同，公共存储器宏也可以安装在半导体集成电路上。 因此，当设计系统时，可以减少半导体集成电路的设计验证时间，评估时间和测试时间。 结果，可以减少半导体集成电路的设计时间和设计成本。

公开(公告)号：US07297996B2

公开(公告)日：2007-11-20

申请号：US11298515

申请日：2005-12-12

Applicant: Ayako Sato ,  Masato Matsumiya ,  Satoshi Eto

Inventor： Ayako Sato ,  Masato Matsumiya ,  Satoshi Eto

IPC: H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10811 ,  H01L27/10882 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/1126

Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Abstract translation: 一种双电池型半导体存储器件，其中芯片的面积可以减小。 在用于将至少一对存储单元中的数据作为补充信息存储的双电池型半导体存储器件中，存储单元以位线位置的间隔排列在多个字线的每一个上。 至少存储有互补信息并且表示多个区域的存储单元对中的每一个连接到一对位线，形成双胞胎。

公开(公告)号：US07243274B2

公开(公告)日：2007-07-10

申请号：US11206170

申请日：2005-08-18

Applicant: Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

Inventor： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

IPC: G11C29/00

CPC classification number: G11C29/48 ,  G11C29/36

Abstract: An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

Abstract translation: 外部终端接收外部信号以访问第一和第二存储器芯片。 当第一和第二存储器芯片正常工作时，测试启动终端接收到测试启动信号，当第一或第二存储器芯片被测试和非激活时激活。 访问信号发生器将外部信号转换为第一存储器芯片的存储器访问信号。 第一选择器在激活测试启动信号期间选择作为测试信号的外部信号，在测试启动信号失效期间选择存储器访问信号。 也就是说，在测试模式期间，可以从外部直接访问第一存储器芯片。 因此，在半导体器件的组装之后，用于单独测试第一存储器芯片的测试程序可以作为测试程序转移。

公开(公告)号：US07203115B2

公开(公告)日：2007-04-10

申请号：US11265229

申请日：2005-11-03

Applicant: Satoshi Eto

Inventor： Satoshi Eto

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618 ,  G11C29/52 ,  G11C2207/104 ,  G11C2211/4061 ,  G11C2211/4062 ,  G11C2211/4067

Abstract: A data additional circuit adds plural types of expectation data to be read from a refresh block to data read from other blocks, respectively, to generate plural read data strings. An error correction circuit detects errors for each read data string, and sets the most reliable result of the error detection results to be true. The error correction circuit decodes data to be read from the refresh block based on a true error detection result. Moreover, the error correction circuit corrects the error of the read data string corresponding to the true error detection result. Consequently, without extending the read cycle time, a refresh operation can be hid, and errors can be corrected simultaneously. By correcting a data error read from a bad memory cell of data retention characteristics, a refresh request interval can be extended, and power consumption during a standby period can be reduced.

Abstract translation: 数据附加电路分别将多个类型的期望数据从刷新块添加到从其他块读取的数据，以产生多个读取数据串。 纠错电路检测每个读取数据串的错误，并将错误检测结果的最可靠的结果设置为真。 错误校正电路根据真实的错误检测结果对从刷新块读出的数据进行解码。 此外，纠错电路校正与真实错误检测结果对应的读取数据串的错误。 因此，在不延长读取周期时间的情况下，可以隐藏刷新操作，并且可以同时校正错误。 通过校正从数据保持特性的不良存储单元读取的数据错误，可以扩展刷新请求间隔，并且可以减少待机期间的功耗。

公开(公告)号：US20060086951A1

公开(公告)日：2006-04-27

申请号：US11298515

申请日：2005-12-12

Applicant: Ayako Sato ,  Masato Matsumiya ,  Satoshi Eto

Inventor： Ayako Sato ,  Masato Matsumiya ,  Satoshi Eto

IPC: H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/10811 ,  H01L27/10882 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/1126

Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Abstract translation: 一种双电池型半导体存储器件，其中芯片的面积可以减小。 在用于将至少一对存储单元中的数据作为补充信息存储的双电池型半导体存储器件中，存储单元以位线位置的间隔排列在多个字线的每一个上。 至少存储有互补信息并且表示多个区域的存储单元对中的每一个连接到一对位线，形成双胞胎。

公开(公告)号：US20050052935A1

公开(公告)日：2005-03-10

申请号：US10968072

申请日：2004-10-20

Applicant: Toshiya Miyo ,  Toshikazu Nakamura ,  Satoshi Eto

Inventor： Toshiya Miyo ,  Toshikazu Nakamura ,  Satoshi Eto

IPC: G11C11/4097 ,  G11C8/00

CPC classification number: G11C11/4097

Abstract: Second memory cells of a second memory block each have an area 2a times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.

Abstract translation: 第二存储器块的第二存储器单元各自具有第一存储器块的每个第一存储器单元的区域2。 以预定比例对第一和第二存储器单元进行尺寸可以使得第一存储块和第二存储块的尺寸容易相同。 因此，可以容易地将外围电路对准在诸如解码器之类的多个第一和第二存储器块周围。 这也有助于连接到外围电路的信号线的布线。 这使得可以提高半导体集成电路的布局设计效率。 因此，可以有效地在半导体集成电路上形成多种类型的存储块。 由于布局简单，可以防止半导体集成电路因布局设计而增加芯片尺寸。

公开(公告)号：US06671220B2

公开(公告)日：2003-12-30

申请号：US10096425

申请日：2002-03-13

Applicant: Akira Kikutake ,  Satoshi Eto

Inventor： Akira Kikutake ,  Satoshi Eto

IPC: G11C800

CPC classification number: G11C7/1093 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/1087

Abstract: A semiconductor device includes input circuits which capture respective data pieces from an exterior of the device in synchronization with respective clock signals supplied from the exterior of the device, a pulse signal generation circuit which generates a pulse signal, and drive circuits which supplies the respective data pieces captured by the input circuits to internal circuitry at a unified timing corresponding to the pulse signal.

Abstract translation: 半导体器件包括输入电路，其与从器件的外部提供的各个时钟信号同步地从器件的外部捕获相应的数据片，产生脉冲信号的脉冲信号产生电路以及提供各个数据的驱动电路 输入电路在对应于脉冲信号的统一定时对内部电路进行捕捉。

公开(公告)号：US06628564B1

公开(公告)日：2003-09-30

申请号：US09339855

申请日：1999-06-25

Applicant: Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

Inventor： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC: G11C808

CPC classification number: G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

Abstract: A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.

Abstract translation: 半导体器件包括字线驱动电路，通过驱动连接到存储单元的字线并在字线的复位操作时切换字线驱动电路的复位电平来重置字线。 此外，半导体器件包括通过布置多个存储单元形成的存储单元阵列和用于选择第一电位或第二电位的复位电平开关电路，并将第一电位或第二电位提供给字线驱动电路。