公开(公告)号：US08692926B2

公开(公告)日：2014-04-08

申请号：US12938994

申请日：2010-11-03

Applicant: Satoshi Eto ,  Senshu Igarashi

Inventor： Satoshi Eto ,  Senshu Igarashi

IPC: H04N5/232 ,  G03B13/00

CPC classification number: H04N5/23212 ,  H04N5/2353

Abstract: A circuit for auto-focus adjustment includes a calculating unit configured to calculate an indicator of randomness of pixel values in a captured image, a direction determining unit configured to compare a first value of the indicator calculated by the calculating unit in a preceding focus adjustment process with a second value of the indicator calculated by the calculating unit after the calculation of the first value, thereby to determine a direction of focus shift in response to a result of the comparison, and a control unit configured to start a focus adjustment process by which a focus position is first moved in the direction of focus shift determined by the direction determining unit.

Abstract translation: 一种用于自动对焦调整的电路包括：计算单元，被配置为计算拍摄图像中的像素值的随机性的指标;方向确定单元，被配置为将由所述计算单元计算出的指标的第一值与先前的焦点调整处理 在计算第一值之后由计算单元计算出的指示符的第二值，从而根据比较结果确定焦点偏移的方向，以及控制单元，其被配置为开始焦点调整处理，通过该调整处理， 首先在由方向确定单元确定的聚焦偏移的方向上移动聚焦位置。

公开(公告)号：US20100220540A1

公开(公告)日：2010-09-02

申请号：US12718808

申请日：2010-03-05

Applicant: Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

Inventor： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

公开(公告)号：US07706209B2

公开(公告)日：2010-04-27

申请号：US11313963

申请日：2005-12-22

Applicant: Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

Inventor： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC: G11C8/08

CPC classification number: G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

Abstract: A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.

Abstract translation: 一种半导体器件，包括用于驱动连接到存储单元阵列中的存储单元的字线的字线驱动器，以及当存储器单元从激活状态变为待机状态时重新设定字线。 当执行字线的复位时，字线驱动器的复位电平被设置，并且可以在第一和第二电位之间切换。 字线复位电平发生电路根据存储单元阵列工作条件改变负电位电流供给量。 半导体器件包括多个电源电路，每个电源电路具有振荡电路和电容器，用于经由振荡电路输出的振荡信号来驱动电容器。 至少一些电源电路共用一个共同的振荡电路，而不同的电容通过公共振荡信号驱动。

公开(公告)号：US07630268B2

公开(公告)日：2009-12-08

申请号：US11450472

申请日：2006-06-12

Applicant: Satoshi Eto

Inventor： Satoshi Eto

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40603 ,  G11C11/40618

Abstract: A dynamic semiconductor memory has a plurality of memory blocks and a memory core. Each of the memory blocks has a sense amplifier, and the memory core is formed from memory cells located at intersections between a plurality of word lines and a plurality of bit lines connected to the sense amplifier. The memory blocks are sequentially refreshed by selecting each of the word lines and by simultaneously activating the memory cells connected to the selected word line by the sense amplifier. The dynamic semiconductor memory has a first refresh counter which outputs a first internal refresh candidate address, and a second refresh counter which outputs a second internal refresh candidate address that is different from the first internal refresh candidate address. When an externally accessed address coincides with the first internal refresh candidate address, a refresh operation is performed starting from the second internal refresh candidate address.

Abstract translation: 动态半导体存储器具有多个存储器块和存储器核。 每个存储块具有读出放大器，并且存储器核心由位于多个字线与连接到读出放大器的多个位线之间的交点处的存储器单元形成。 通过选择每个字线并且通过感测放大器同时激活连接到所选择的字线的存储器单元来顺序刷新存储器块。 动态半导体存储器具有输出第一内部刷新候补地址的第一刷新计数器和输出与第一内部刷新候补地址不同的第二内部刷新候补地址的第二刷新计数器。 当外部访问的地址与第一内部刷新候选地址一致时，从第二内部刷新候选地址开始执行刷新操作。

公开(公告)号：US07072243B2

公开(公告)日：2006-07-04

申请号：US10965951

申请日：2004-10-18

Applicant: Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

Inventor： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

IPC: G11C8/00

CPC classification number: G11C11/40603 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2281 ,  G11C2211/4061

Abstract: A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

公开(公告)号：US20060136800A1

公开(公告)日：2006-06-22

申请号：US11088940

申请日：2005-03-25

Applicant: Kuninori Kawabata ,  Satoshi Eto ,  Yasuhiro Onishi ,  Akira Kikutake

Inventor： Kuninori Kawabata ,  Satoshi Eto ,  Yasuhiro Onishi ,  Akira Kikutake

IPC: G11C29/00

CPC classification number: G06F11/1012

Abstract: A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection circuit references one redundant bit added to the parity bits, detects a double-bit error, and enables or disables the double-bit error detection in accordance with a selection signal.

Abstract translation: 一种可以在不增加芯片尺寸并且不降低访问时间的情况下提高产量的存储系统。 单位错误确定电路参考配置能够校正单位错误的代码所需的奇偶校验位，并确定要纠正的单位错误; 并且双位错误检测电路参考添加到奇偶校验位的一个冗余位，检测双位错误，并且根据选择信号启用或禁用双位错误检测。

公开(公告)号：US07064998B2

公开(公告)日：2006-06-20

申请号：US11215045

申请日：2005-08-31

Applicant: Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

Inventor： Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo

IPC: G11C7/00

CPC classification number: G11C11/40603 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2281 ,  G11C2211/4061

Abstract: A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

Abstract translation: 定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。 外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。 预定时间被设定为比存储器芯执行单次操作的核心操作时间长。 因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。 因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

公开(公告)号：US06339345B1

公开(公告)日：2002-01-15

申请号：US09696048

申请日：2000-10-26

Applicant: Satoshi Eto ,  Hironobu Akita ,  Katsuaki Isobe

Inventor： Satoshi Eto ,  Hironobu Akita ,  Katsuaki Isobe

IPC: H03L700

CPC classification number: G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/2254 ,  H03K5/135 ,  H03K19/00384 ,  H03L7/00

Abstract: In an output circuit 10, a latch circuit 11, a phase difference controlled circuit 12 and an output buffer circuit 13 are cascaded and a DATA is clocked into the latch circuit 11. A replica circuit 20 is a down-scaled version of a layout pattern of the output circuit 10, comprises circuits 21 to 23 corresponding to the circuits 11, 12 and 13, and a CLK is provided through a delay circuit 5 and a divide-by-2 frequency divider 16 to the data input of the latch circuit 21 as a data. The output of the replica circuit 20 is provided through a dummy load circuit 24 and a low pass filter 25 to a comparator 26, the output thereof is compared with a reference voltage Vref to generate count-up or count-down pulses. The pulses are counted by an up-down counter 27 whose count is provided to the phase difference controlled circuit 12 and its replica 22 to reduce the phase difference between rising and falling edges of the output signal of the output buffer circuit 23.

Abstract translation: 在输出电路10中，锁存电路11，相位差控制电路12和输出缓冲器电路13级联，并且DATA被锁定到锁存电路11中。复制电路20是布局模式的缩小版本 输出电路10包括对应于电路11,12和13的电路21至23，并且通过延迟电路5和分频2分频器16将CLK提供给锁存电路21的数据输入 作为数据。 复制电路20的输出通过虚拟负载电路24和低通滤波器25提供给比较器26，其输出与参考电压Vref进行比较，以产生递增计数或递减计数脉冲。 脉冲由计数器27计数，该计数器的计数被提供给相位差控制电路12及其副本22，以减小输出缓冲电路23的输出信号的上升沿和下降沿之间的相位差。

公开(公告)号：US06333658B1

公开(公告)日：2001-12-25

申请号：US09707791

申请日：2000-11-08

Applicant: Hironobu Akita ,  Satoshi Eto ,  Katsuaki Isobe ,  Masaharu Wada ,  Haruki Toda

Inventor： Hironobu Akita ,  Satoshi Eto ,  Katsuaki Isobe ,  Masaharu Wada ,  Haruki Toda

IPC: H03H1126

CPC classification number: H03K5/135

Abstract: An analog synchronization circuit includes an input buffer which is supplied with an external clock signal, a delay monitor which is supplied with a clock signal output from the input buffer, an output buffer for outputting a clock signal synchronous with the external clock signal and two charge balance delay circuits. The two charge balance delay circuits are equivalent to delay lines in a mirror type delay locked loop. Each charge balance delay circuits operates once in two consecutive cycles of the external clock signal. The two charge balance delay circuits alternately operate and output signals of the charge balance delay circuits are supplied to the output buffer via an OR gate. First and second capacitors are provided in each charge balance delay circuits. A first current source circuit charges the first capacitor for a time equivalent to a delay time of a forward pulse. The second capacitor is charged by a second current source circuit. A comparator compares charge voltages of the first and second capacitors with each other and generates a timing signal when both charge voltages coincide with each other.

Abstract translation: 模拟同步电路包括被提供有外部时钟信号的输入缓冲器，被提供有从输入缓冲器输出的时钟信号的延迟监视器，用于输出与外部时钟信号同步的时钟信号的输出缓冲器和两个充电 平衡延迟电路。 两个电荷平衡延迟电路等效于镜像延迟锁定环路中的延迟线。 每个电荷平衡延迟电路在外部时钟信号的两个连续周期中运行一次。 两个电荷平衡延迟电路交替工作，并且电荷平衡延迟电路的输出信号通过或门提供给输出缓冲器。 在每个电荷平衡延迟电路中提供第一和第二电容器。 第一电流源电路对第一电容器充电等于正向脉冲的延迟时间的时间。 第二电容器由第二电流源电路充电。 比较器将第一和第二电容器的充电电压彼此进行比较，并且当两个充电电压彼此一致时产生定时信号。

公开(公告)号：US06169701A

公开(公告)日：2001-01-02

申请号：US08946586

申请日：1997-10-07

Applicant: Satoshi Eto ,  Masato Matsumiya ,  Hideki Kanou

Inventor： Satoshi Eto ,  Masato Matsumiya ,  Hideki Kanou

IPC: G11C800

CPC classification number: G11C7/065

Abstract: In the present invention, the gate electrodes of the bit line transfer gates for bit line pair selection that perform connection and isolation of the sense amplifiers and bit line pairs are put into floating condition during activation of the sense amplifier in the active period. Thus, a system is adopted according to which the potential of the bit line is driven to power source voltage Vcc or high voltage corresponding thereto by the sense amplifier in the active condition, the pre-charging potential of the bit line pair being made lower than half the power source voltage Vcc, for example ground potential Vss. Thanks to the amplification action of the sense amplifier, by utilising the fact that one side of the plurality of bit line pairs is inevitably driven from low potential to the power source voltage Vcc level or high voltage corresponding thereto, the potential of the gate electrodes which are in floating condition is boosted higher due to capacitative coupling, enabling the potential of the bit line on rewriting to be boosted to a voltage driven by the sense amplifier, for example power source voltage.

Abstract translation: 在本发明中，在激活期间的感测放大器的激活期间，执行读出放大器和位线对的连接和隔离的位线对选择的位线传输门的栅极被置于浮置状态。 因此，采用一种系统，根据该系统，位线的电位在激活状态下由读出放大器驱动到电源电压Vcc或与其对应的高电压，位线对的预充电电位低于 电源电压Vcc的一半，例如地电位Vss。 由于读出放大器的放大动作，通过利用多个位线对的一侧不可避免地从低电位驱动到对应于其的电源电压Vcc电平或高电压的事实，栅电极的电位 处于浮置状态的电容由于电容耦合而被提升得更高，使得重写中的位线的电位可以升高到由读出放大器驱动的电压，例如电源电压。