Invention Grant
- Patent Title: CMOS compatible process with different-voltage devices
- Patent Title (中): CMOS兼容过程与不同电压器件
-
Application No.: US10914943Application Date: 2004-08-09
-
Publication No.: US07205201B2Publication Date: 2007-04-17
- Inventor: Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
- Applicant: Chih-Feng Huang , Ta-yung Yang , Jenn-yu G. Lin , Tuo-Hsin Chien
- Applicant Address: TW Taipei Hsien
- Assignee: System General Corp.
- Current Assignee: System General Corp.
- Current Assignee Address: TW Taipei Hsien
- Agency: J.C. Patents
- Main IPC: H01L21/8234
- IPC: H01L21/8234

Abstract:
A method of manufacturing different-voltage devices mainly comprises forming at least one high-voltage well in high-voltage device regions, at least one N-well in low-voltage device regions, at least one P-well in low-voltage device regions, source/drain wells in high-voltage device regions, and isolation wells in isolation regions in a p-type substrate. The breakdown voltage is adjusted by modulating the ion doping profile. Furthermore, parameters of implanting conductive ions are adjusted for implanting conductive ions into both high-voltage device regions and low-voltage device regions. The isolation wells formed in isolation regions between devices are for separating device formed over high-voltage device regions and device formed over low-voltage device regions. The thickness of a HV gate oxide layer is thicker than the thickness of an LV gate oxide layer for modulating threshold voltages of high-voltage devices and low-voltage devices.
Public/Granted literature
- US20060030107A1 CMOS compatible process with different-voltage devices Public/Granted day:2006-02-09
Information query
IPC分类: